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May 27, 2024 - Java
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An open source, parameterized SystemVerilog digital hardware IP library
IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
My digital design portfolio website (WIP)
Designing Single-Cycle Microprocessor without Interlocked Pipeline Stages (MIPS) using Verilog.
UART Transmitter and Receiver implementation for FPGA
Pre and Post Synthesis Simulation of a Design VSDMemSOC
online portfolio
Fundamentals of Digital Logic with Verilog Design by Stephen Brown and Zvonko Vranesic, 3rd Edition.
RISC-V single-cycle processor written in Verilog using the Quartus tool. Implementation of bubble sort through assembly language.
AdobeAllInOne is a comprehensive suite of creative software tools developed by Adobe. It includes a range of applications for design, photography, video editing, and more, making it the ultimate solution for all your creative needs.
Course Project - Microprocessors - Spring Semester 2022 - Indian Institute of Technology Bombay
Python script for generating lookup tables for the gm/ID design methodology and much more ...
VHDL-by-HGB is a VS-Code extension for VHDL.
A simple Floating-Point arithmetic unit - implemented in SystemVerilog
Basic digital designs developed with Verilog and VHDL.
Transpiles a subset of Python functions into synthesizable SystemVerilog.
This is "In Progress" Repo for all the beginners who want to learn Digital Design using Verilog HDL.
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