axi4
Here are 48 public repositories matching this topic...
VeeR EL2 Core
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Jun 4, 2024 - SystemVerilog
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
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May 29, 2024 - VHDL
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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May 27, 2024 - SystemVerilog
Common SystemVerilog RTL modules for RgGen
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May 15, 2024 - SystemVerilog
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
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May 4, 2024 - SystemVerilog
RISCV CPU implementation in SystemVerilog
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Apr 25, 2024 - Coq
RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
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Apr 7, 2024 - Verilog
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
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Dec 6, 2023 - VHDL
Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.
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Aug 3, 2023 - VHDL
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
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Jun 26, 2023 - SystemVerilog
VeeR EH1 core
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May 29, 2023 - SystemVerilog
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
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Sep 21, 2022 - VHDL
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