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@oscc-ip

OSCC IP Project

Develop and maintain IP Projects under OSCC (Open Source Chip Community).

OSCC IP: A series of Verified HDL IP with Accurate-cycle and Event-driven Model

Hi, OSCC IP Project 👋

OSCC IP Project contains a bundle of IPs which aim to improve development experience of processor and SoC design. Now it mainly focus on frontend and verification field. We hope it can be integrated by other components to build a common workflow for agile hardware development from frontend to backend one day.

Motivation

IPs list and development state:

IP MILESTONE
archinfo
rng
sram
ps2
clint
pwm
timer
wdg
rtc
uart
i2c
spi
i2s
vga
More Info

Template

Refer to the template repo. If you want to create a new ip repo, You need to:

  • Use this repository template to create a new repo
  • Update the content [IP NAME] in header file and remove the header file.

Style

refer to the style.md.

Contribution

If you want to contribute to this project, be sure to review the guidelines. This is an open project and contributions and collaborations are always welcome!! This project adheres to OSCC IP's code_of_conduct. By participating, you are expected to uphold this code.

we use GitHub issues for tracking requests and bugs, so please direct specific questions to issues panel.

The OSCC IP project strives to abide by generally accepted best practices in open-source software development, you can issue bugs, pull requests, new features and modification suggestions freely. Your feedbacks could help us ensure a bright future for this project. We value and treasure every issue or contribution, big or small. 😄

License

All of the IPs codes are redistributed or released under the OSI Approved LICENSE MulanPSL2.

Acknowledgement

Reference

Pinned

  1. sdram sdram Public

    An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

    Makefile 7 1

  2. vga vga Public

    An AXI4-based VGA Controller

    SystemVerilog 3

  3. gpio gpio Public

    An APB4-based GPIO Controller

    SystemVerilog 1

  4. timer timer Public

    An APB4-based Timer Controller

    SystemVerilog 1

  5. common common Public

    A SystemVerilog Components Library

    SystemVerilog 1

  6. sram sram Public

    An AXI4-based SRAM Controller

    SystemVerilog 4

Repositories

Showing 10 of 25 repositories
  • .github Public
    1 GPL-3.0 0 0 0 Updated May 9, 2024
  • i2s Public

    An APB4-based I2S Controller

    SystemVerilog 0 MulanPSL-2.0 0 0 0 Updated May 9, 2024
  • spi Public

    An APB4-based SPI Controller

    SystemVerilog 2 MulanPSL-2.0 0 0 0 Updated May 9, 2024
  • psram Public

    An AXI4-based PSRAM Controller

    SystemVerilog 0 MulanPSL-2.0 0 0 0 Updated May 7, 2024
  • i2c Public

    An APB4-based I2C Controller

    SystemVerilog 1 MulanPSL-2.0 0 0 0 Updated May 6, 2024
  • uart Public

    An APB4-based UART Controller

    SystemVerilog 2 MulanPSL-2.0 0 1 0 Updated May 4, 2024
  • common Public

    A SystemVerilog Components Library

    SystemVerilog 1 MulanPSL-2.0 0 0 0 Updated May 1, 2024
  • sram Public

    An AXI4-based SRAM Controller

    SystemVerilog 4 MulanPSL-2.0 0 1 0 Updated Apr 22, 2024
  • gpio Public

    An APB4-based GPIO Controller

    SystemVerilog 1 MulanPSL-2.0 0 0 0 Updated Apr 22, 2024
  • wdg Public

    An APB4-based WatchDog Controller

    SystemVerilog 1 MulanPSL-2.0 0 0 0 Updated Apr 22, 2024

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