Skip to content

Issues: chipsalliance/Cores-VeeR-EL2

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

28 Open 45 Closed
28 Open 45 Closed
Author
Filter by author
Label
Filter by label
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Milestones
Filter by milestone
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

EL2_DMA_CTRL.sv AXI interface the burst length mode, awlen & arlen is not used, it is Error ?
#169 opened May 13, 2024 by xiaolei-cheng
Relation between Core reset(rst_l) and dbg_rst_l
#168 opened Apr 27, 2024 by Syed-mudabbir-ahsan
Request to review Lint Issues in Veer RTL
#166 opened Apr 6, 2024 by amullick007
FuseSoC core description file is missing
#165 opened Mar 27, 2024 by olofk
Does this design work with VCS/Cadence/Mentor simulators after memories were moved from design to tb_top?
#163 opened Mar 3, 2024 by algrobman
LHS lesser than RHS : el2_ifu_mem_ctl.sv : ic_debug_way
#161 opened Mar 1, 2024 by nstewart-amd
Caliptra JTAG TdoEn missing output
#159 opened Feb 9, 2024 by nstewart-amd
2
Add support for DMI export to system
#148 opened Dec 11, 2023 by calebofearth
Remove (or make optional) the JTAG IDCODE command
#146 opened Dec 11, 2023 by calebofearth
6
SRAM instance export
#145 opened Dec 11, 2023 by calebofearth
2
compile fail with TEST=dhry
#136 opened Nov 21, 2023 by hbhbts
1
Issue with dhry test
#107 opened Aug 21, 2023 by cartersmith15
1
Two State Logic LINT violations - el2_pdef.vh
#105 opened Aug 14, 2023 by nstewart-amd
WFI instruction is missing?
#104 opened Jul 5, 2023 by Risto97
Replacing hand instantiated synchronizer flops
#103 opened Jun 30, 2023 by nstewart-amd
1
Next PC not sampled when core wakes up from sleep in Verilator run
#88 opened Jun 7, 2023 by upadhyayulakiran
4
VeeR defines uniquification
#59 opened Feb 17, 2023 by nstewart-amd
RV_ASSERT_ON is always enabled
#58 opened Feb 17, 2023 by nstewart-amd
5
EL2 Memory Interface ​Synthesis Compatibility
#57 opened Feb 17, 2023 by nstewart-amd
synchronizers implemented as synthesizable flops
#51 opened Jan 18, 2023 by rahuljainNV
3
Replacing hand instantiated clock gate cells
#50 opened Jan 18, 2023 by rahuljainNV
9
Hiding assertions code from design tools
#49 opened Jan 18, 2023 by rahuljainNV
12
branch prediction understanding
#40 opened Mar 27, 2022 by KinzaQamar
display statement in el2_ifu.sv
#39 opened Mar 25, 2022 by KinzaQamar
6
understanding Branch Prediction
#37 opened Dec 12, 2021 by KinzaQamar
ProTip! Follow long discussions with comments:>50.