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altera-fpga

Here are 57 public repositories matching this topic...

MUDAL / Altera_FPGA_Projects

This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.

fpga electronics vhdl stm32 embedded-systems modelsim quartus-prime altera-fpga rtl-design-and-verification

Updated May 31, 2024
C

TanumaHideki / ReLM-PoC

ReLM is the soft-core multiprocessor technology based on the unique memory architecture, enabling users to build a high-performance microcontroller on a relatively small FPGA board.

game python fpga multiprocessing parallel parallel-computing verilog altera parallel-processing multiprocessor softcore altera-fpga relm register-less bubble-estate

Updated May 23, 2024
Python

Multimedia-Processing / Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Updated Oct 25, 2023
Verilog

HaochengBillYang / ece385

ECE385 @ UIUC FA22

systemverilog altera-fpga uiuc-ece

Updated Oct 10, 2023
Verilog

mrLSD / fpga

Research & Development FPGA projects for different boards

fpga verilog systemverilog altera-fpga sipeed-tang-nano-9k

Updated Oct 1, 2023
GLSL

gaikwadabhishek / flappy-bird-fpga-vhdl

Flappy Bird on FPGA using VHDL

fpga vhdl flappy-bird altera-fpga fpga-programming cyclone-ii

Updated May 2, 2023
HTML

asankaSovis / Position_Detection

📌 The idea of this project is to build a system that uses the existing lights to detect the location of a user within an indoor environment. For this, we can use Visible Light Communication (VLC) technology. The basic concept is to have four LEDs transmitting their IDs one after the other at fixed intervals.

c-sharp arduino fpga intel visible-light-communication uart-protocol serial-communication altera-fpga

Updated Apr 27, 2023
Verilog

william-hazem / LASD

Laboratório de Arquitetura de Sistemas Digitais, ministrado pelo professor Rafael Bezerra Correia Lima. Foram desenvolvidos 8 requisitos de hardware, 1 requisito de software e 1 projeto de disciplina que totalizam 10 Sprints. A arquitetura de sistemas implementada é baseada em MIPS 8 bits, e desenvolvidos e testados na FGPA Ciclone II EP2C35F672C6

mips verilog altera-fpga

Updated Feb 9, 2023
Verilog

Chrisdeleon91 / Altera-DE1-VGA-Interface

Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.

fsm vhdl intel finite-state-machine quartus-prime vga-driver vga-controller altera-fpga vhdl-coursework quartus2 altera-de1

Updated Feb 7, 2023
VHDL

XAli-SHX / Implementation-of-an-Edge-Detection-Filter-Using-the-Avalon-Interface

Implementation of an Edge Detection Filter Using the Avalon Interface

fpga verilog edge-detection avalon sobel quartus altera-fpga sobel-filter rgb2gray sobel-edge-detector avalon-bus avalon-streaming

Updated Jan 30, 2023
Verilog

atmughrabi / AccelGraph

Graph Processing Framework that supports || OpenMP || CAPI

Updated Jan 21, 2023
SystemVerilog

mohamedtareq24 / 4_Channel_Logic_Analyzer

FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA

fpga verilog logic-analyzer quartus-prime altera-fpga

Updated Nov 21, 2022
Verilog

M-Schrapel / FPGA-Function-Generator

A scalable and freely configurable function generator in VHDL

open-source fpga vr vhdl virtual-reality open-science hci human-computer-interaction function-generator actuator-control tactile-feedback altera-fpga papers-with-code tactile-perception

Updated Nov 20, 2022
VHDL

briansune / Altera-Cyclone-V-HDMI

Verilog based HDMI for Cyclone V or Altera series

verilog hdmi cyclone-v altera-fpga tmds

Updated Oct 4, 2022
Verilog

MinhTran0911 / UART_DE10

UART Receiver and Transmitter using Terasic DE-10 Standard FPGA

uart systemverilog hdl modelsim quartus-prime hardware-description-language altera-fpga terasic-de10-standard

Updated Aug 4, 2022
SystemVerilog

MinhTran0911 / Simple_CPU_DE10

Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA

cpu fpga systemverilog hdl modelsim quartus-prime cyclone-v hardware-description-language altera-fpga terasic-de10-standard

Updated Aug 3, 2022
SystemVerilog

MinhTran0911 / Stopwatch_DE10

Basic Stopwatch Design using Terasic DE-10 Standard FPGA

systemverilog hdl modelsim quartus-prime cyclone-v hardware-description-language altera-fpga terasic-de10-standard

Updated Jul 30, 2022
SystemVerilog

MinhTran0911 / DS1302_Interface_DE10

DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA

ds1302 systemverilog hdl modelsim quartus-prime cyclone-v rtc-module hardware-description-language altera-fpga terasic-de10-standard

Updated Jul 30, 2022
SystemVerilog

sbaldzenka / random_number_generator

c linux verilog questasim fpga-soc altera-fpga

Updated Jun 16, 2022
Verilog

t4rcisio / Arquivos_Verilog

Processador nano-Risc, controlaor de display, e muito mais...

fpga vhdl intel verilog quartus altera-fpga

Updated Apr 2, 2022
Verilog

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