Academic projects created using Assembly, in the Intel FPGA Monitor Program, for the laboratory work done while attending the McGill Course ECSE 324 Computer Organization
-
Updated
Jan 3, 2022 - Assembly
Academic projects created using Assembly, in the Intel FPGA Monitor Program, for the laboratory work done while attending the McGill Course ECSE 324 Computer Organization
A simple processor designed using Verilog and Altera DE1 development board.
Pin file in .qsf format for Altera DE1 FPGA
A simple sram controller and test for the altera DE1 FPGA board
Using finite state machine (FSM) approach to design a traffic light controller on Altera DE1 development board.
Synthesize a general purpose microprocessor (GPM) using verilog hdl code on Altera DE1 development board. The processor was used to find the greatest common divisor (GCD) between two integers.
The Snake Game Made in VHDL for Altera DE1 using Quartus V.13
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board
Helps with Cross compilation for arm-gnueabihf-gcc linux compilation for the HPS found in cyclone V subsystems on DE1-SOC boards.
Kitchen-timer on Altera DE1 FPGA development kit - VHDL
Add a description, image, and links to the altera-de1 topic page so that developers can more easily learn about it.
To associate your repository with the altera-de1 topic, visit your repo's landing page and select "manage topics."