Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Implement riscv_vlen_asm for riscv32 #24270

Closed
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Jump to
Jump to file
Failed to load files.
Diff view
Diff view
17 changes: 17 additions & 0 deletions crypto/riscv32cpuid.pl
Expand Up @@ -84,5 +84,22 @@
___
}

{
my ($ret) = ('a0');
$code .= <<___;
################################################################################
# size_t riscv_vlen_asm(void)
# Return VLEN (i.e. the length of a vector register in bits).
.p2align 3
.globl riscv_vlen_asm
.type riscv_vlen_asm,\@function
riscv_vlen_asm:
csrr $ret, vlenb
slli $ret, $ret, 3
ret
.size riscv_vlen_asm,.-riscv_vlen_asm
___
}

print $code;
close STDOUT or die "error closing STDOUT: $!";