NetFPGA 1G CML FAQ
Part 1 Operating Systems and Xilinx Tools
Q: Are there any particular OS and Xilinx packages I should have installed before I get started:
A: Yes. We have have used Fedora 20 (x86_64) and Xilinx ISE Design Suite 14.6, although later versions should also work.
Note that the Kintex XC7K325T is not supported by the freely-downloadable Xilinx Webpack.
If you are affiliated with a univeristy, check with your system administrators to see if they already have a Xilinx university licensing agreement in place. If they do not, you may wish to request that they contact the Xilinx University Program for more details.
If you are not affiliated with a university, you can obtain a 30-day ISE/EDK design suite evaluation license from Xilinx that includes everything you need to re-generate the bitstreams. The least expensive permanent solution is to purchase a node locked ISE/EDK design suite from Avnet.
It is also possible to port the reference designs to Xilinx's more advanced Vivado Design Suite, and depending on your objectives, that may provide the best long term solution.
Q: Are there any other things I should do before I begin?
A: Please read the NetFPGA-1G-CML Reference Manual page, which provides information pertaining to the CML NetFPGA Design
Q: I am getting the error 'Module windrvr6 is not loaded. Please reinstall the cable drivers. What can I do?
A: Perform the setup described at the link: Fixing Windrvr6 Error in Xilinx
Part 2 NetFPGA-1G-CML Codebase
Q: Have all previous NetFPGA-1G projects been ported to the NetFPGA-1G-CML Project.
A: The following NetFPGA-10G projects have been ported to NetFPGA-1G-CML: loopback_test, reference_nic, reference_switch_lite, reference_switch, and reference_router.
Q: Were the NetFPGA-1G-CML projects derived directly from the original NetFPGA-1G projects?
A: No. The NetFPGA-1G-CML projects were derived from the more recent NetFPGA-10G projects. The original NetFPGA-1G projects were organized differently and were developed using Fedora-13 and Xilinx 10.1. The NetFPGA-1G-CML projects have been developed using Fedora-20 and Xilinx ISE/EDK 14.6, as mentioned in Part 1: Operating Systems.
Q: Does the 7-series FPGA support the CAM generator used on the Virtex-5?
A: Yes, please the README file for the reference_switch and reference_router projects.
Part 3 NetFPGA-1G-CML Hardware
Q: Does the NetFPGA-1G-CML have to be installed into a host's PCIe socket for development?
A: No. The NetFPGA-1G-CML can be used in either a stand-alone mode or installed into a host PCIe slot. The stand-alone mode requires power from an ATA power connector and cables for the JTAG connection and UART connection via the PMOD connector. See photos below.
Figure 1 - NetFPGA 1G CML Standalone Mode
Figure 2 - NetFPGA 1G CML PCIe Mode
Q: Does the PCIe mode require a specific PCIe driver?
A: Yes. The specific Linux driver to access the card while in PCIe mode is located at /projects/reference_nic_nf1_cml/sw/host/driver. Run the Makefile while in that directory [make]. The Makefile will create the nf10.ko file. The nf10.ko can be installed by running the following command [sudo insmod nf10.ko].
Note: The NetFPGA card must be loaded with correct bit stream to operate in PCIe mode. The computer will need to be restarted after loading the bitstream. After restarting the computer, run the command [lspci] and the Xilinx card should be visible with VendorID 0x10ee and ProductID 0x4244.
* How to test the PCIe interface using the internal loopback on a standalone machine.
* Go to the directory /projects/reference_nic_nf1_cml/sw/host/driver
* Edit nf10priv.c by enabling the #define LOOPBACK variable then recompile driver
* Install the re-compiled driver [sudo insmod nf10.ko]
* Perform the ifconfig and arp setting modifications to nf0 and nf3 as outlined in nf10priv.c.
* Connect cable between nf0 and nf3; nf0 is the port located nearest to the PCIe connector.
* Performed the ping outlined in nf10priv.c; ping 192.168.2.12
Q: How should the UART be configured for testing the NetFPGA 1G CML board?
A: CML has adopted Minicom for serial communication with the NetFPGA 1G CML board. The UART is accessed using a PmodUSBUART and is seen in the pictures connected to the PMOD connector.
* Minicom requires your user name be added to the dialout group, /etc/group
* Configure Minicom by typing [minicom -s] with setting 115200 8 N 1
* Connect PmodUSBUART to computer using a USB cable, micro(male) to type A (male)
* Type [dmesg | grep tty] to identity the serial port
Q: How is the board tested using the loopback test?
A: The loopback test is located in the projects directory, loopback_test_nf1_cml.
* The pcores must first be created by running [make] in the core directory, NetFPGA-10G-live.
* Change directories to /NetFPGA-10G-live/projects/loopback_test_nf1_cml and run [make].
* Connect the JTAG programming cable to JTAG header and PmodUARTUSB module with USB cable to the PMOD connector.
* Connect one Ethernet cable between ETH1 and ETH2 and another between ETH3 and ETH4.
* After the [make] has successfully completed, run [make download].
* This will download bitfile located in /projects/loopback_test_nf1_cml/bitfiles into the FPGA.
* Upon completion the Minicom terminal should display the test configuration menu as shown in Figure 3.
* Figure 4 shows the board setup for loopback testing.
Figure 3 - Minicom Screen loopback-test-nf1-cml
Figure 4 - NetFPGA 1G CML Loopback Test
Q: How do I correct the following error:
ERROR:EDK - BlackBox Netlist file nf1_cml_interface_v1_00_a/netlist/trimac_lite.ngc not found
A: Go to the NetFPGA-10G-live-cml directory and run the following command 'make cml_cores'.
Q: Is there a fix for reference_switch_lite_nf1_cml and reference_switch_nf1_cml Python hardware tests failing on the first run.
A: Yes, The issue is associated with a service called 'avahi' present on Fedora and Ubuntu which sends out MDNS packets. The service is not required and can be disabled by performing the following for the specific OS:
Fedora: [perform] sudo systemctl disable avahi-daemon.service then rebooting
Ubuntu: [follow instructions] http://askubuntu.com/questions/286035/how-do-i-turn-off-avahi-daemon-on-boot
Q: Does connecting to a design via XMD using the supplied USB cable require a special plug-in for connecting to a Microblaze debug module?
A: Yes, type the following command at the XMD prompt:
XMD% connect mb mdm -cable type xilinx_plugin modulename digilent_plugin
Q: Running "make cores" from the repository root directory generates a series of errors. How can I fix this?
A: The "make cores" rule has been changed to "make cml_cores" for the NetFPGA-1G-CML.
Q: How can I fix an error while running "make" in a project directory indicating the MPD file cannot be found?
ERROR:EDK - IPNAME: nf1_cml_interface, INSTANCE: nf1_cml_interface_0 - cannot find MPD for the pcore
A: Go to the <project_name>/lib folder and perform an 'ls -l'. The contrib and std folders should be symbolic links, as shown below:
* lrwxrwxrwx 1 name name 23 Apr 23 10:03 contrib -> ../../../lib/hw/contrib
* lrwxrwxrwx 1 name name 19 Apr 23 10:03 std -> ../../../lib/hw/std
Extracting the code on a Windows system causes the symbolic links to convert to regular files. This will result in EDK not finding the MPD for th pcores. Convert these folders to symbolic pointing to /lib/hw/ as shown above.
Q: How do I select the MAC used in the nf1_cml_interface and are there license requirements and limitations?
A: The MAC is selected by setting the C_MAC_SEL parameter under the nf1_cml_interface instantiation in system.mhs file. A Xilinx license is required to build either the TRIMAC_LITE or TRIMAC MAC. The UCSD MAC is the default and only works at 1G speeds (not 10 or 100).
* C_MAC_SEL = 0 : Xilinx tri-mode Ethernet MAC with external registers (TRIMAC_LITE)
* C_MAC_SEL = 1 : Xilinx tri-mode Ethernet MAC with internal registers (TRIMAC)
* C_MAC_SEL = 2 : UCSD Ethernet MAC (default)