Discussions

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  Welcome to verilog-ethernet Discussions!

  alexforencich started Dec 11, 2020 in General

  

  

  

  

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  RGMII PHY with fixed link

  dorotheapfeiffer asked Apr 26, 2024 in Q&A · Closed · Answered

  

  

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  Changes to ip_eth_tx_64.v

  EdwinEstep asked Apr 29, 2024 in Q&A · Unanswered

  

  

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  How do I adapt rgmii_phy_if.v for use with Lattice ECP5 primitives for IODDR and Clock input style?

  t1ch asked Mar 24, 2024 in Q&A · Unanswered

  

  

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  eth_mac_phy_10g_fifo missing external serdes_rx_reset_req?

  rconraduw started Feb 23, 2023 in General

  

  

  

  

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  Sniffing UDP packets when phy is used by PS

  catkira asked Feb 15, 2024 in Q&A · Closed · Answered

  

  

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  X3 Port Request

  lotusdew1980 started Feb 19, 2024 in Ideas

  

  

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  2.5G and 5G Support?

  hopethis asked Jan 30, 2024 in Q&A · Unanswered

  

  

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  ZCU106 example design test ,no data return

  JLFu asked Nov 29, 2023 in Q&A · Unanswered

  

  

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  ZCU106 example design test ,no data return

  JLFu asked Nov 29, 2023 in Q&A · Closed · Unanswered

  

  

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  Does this project support SGMII interface now?

  yinyeyy asked Nov 7, 2023 in Q&A · Unanswered

  

  

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  Ethernet for VCU118 with MATLAB

  navidaadit asked Oct 30, 2023 in Q&A · Answered

  

  

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  Intra-frame control characters

  andyu-mhlt asked Sep 21, 2023 in Q&A · Closed · Answered

  

  

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  UDP packet MTU

  MarcoPanconesi started Sep 7, 2023 in General

  

  

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  VCU series FPGA has been widely used.

  qwer872336019 started Aug 21, 2023 in Ideas

  

  

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  Logic clock (MAC)

  MarcoPanconesi started Aug 17, 2023 in General

  

  

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  Why does the checksum add a constant number(2)?

  yinyeyy started Jun 20, 2023 in General

  

  

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  How and where are the inputs given?

  sametzeybek asked Apr 8, 2023 in Q&A · Answered

  

  

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  ZCU102 Vivado build

  kvantumnuly asked Mar 20, 2023 in Q&A · Answered

  

  

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  ZC706 Optical Loopback

  devradu asked Dec 27, 2022 in Q&A · Unanswered

  

  

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  ZCU106 SFP+ example

  elmohandis asked Oct 27, 2022 in Q&A · Answered

  

  

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  0-length UDP payload

  norumwe12 asked Aug 25, 2022 in Q&A · Unanswered

  

  

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  How to make a project file

  omogawa asked May 31, 2022 in Q&A · Unanswered

  

  

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  How to run simulation test benches

  zaidtahirbutt asked May 21, 2022 in Q&A · Answered

  

  

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  How to use this code in inline/passthrough mode instead of loopback on VC 707?

  optiplex91 asked Feb 16, 2022 in Q&A · Unanswered

  

  

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