Update picorv32.v #186
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Update picorv32.v #186
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Clocked process for the AXI_BREADY signal.
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Clocked process for the AXI_BREADY signal.
The BREADY has to go low with BVALID. This was not the case in my simulation. BREADY was one clock cycle longer high than allowed.
Here I propose a bugfix, it worked for me and simulation in Modelsim looks good.
Kind regards
Sebastian