Issues: SpinalHDL/SpinalHDL
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#223
opened Jun 25, 2019 by
Dolu1990
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When’ Requirement: Merging ‘setWhen’ and ‘clearWhen’ in Verilog Output
#1419
opened May 17, 2024 by
dreamflyings
『Help』Component Interface Name Changes Result in SpinalHDL Generating Excessive Redundant Module.v Files.
#1416
opened May 14, 2024 by
dreamflyings
SpinalSim: onSamplings can't work properly with clock from a blackbox
#1334
opened Mar 3, 2024 by
zyn810039594
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
#1314
opened Feb 19, 2024 by
janschiefer
WishboneSlaveFactory - doWrite is never called in pipelined mode
#1310
opened Feb 13, 2024 by
janschiefer
StreamFragmentWidthAdapter.make missing earlylast argument
#1303
opened Feb 6, 2024 by
louiecaulfield
Axi4Stream user signal width should not be multiplied by data width
#1294
opened Jan 23, 2024 by
KireinaHoro
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