Replies: 1 comment 3 replies
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In the first one you use DValid before declaring it. It should fail with an error (null pointer) and not output an incomplete file. Looks like a bug.
Le 30 mars 2023 14:53:32 UTC, Quiz ***@***.***> a écrit :
…### When using History,the following source code:
```
case class SerilIIRV2(Qi: Int) extends Component {
val io = new Bundle {
val input = slave(Flow(SInt(Qi bits)))
val output = out(SInt(16 bits))
}
noIoPrefix()
val YBuffer = History((io.input.payload), 4, DValid, S(0, 16 bits))
val DValid = Reg(Bool()) init (False)
DValid := io.input.valid
io.output := YBuffer(3)
}
```
### Generated verilog:
```
`timescale 1ns/1ps
module SerilIIRV2 (
input input_valid,
input [15:0] input_payload,
output [15:0] output_1,
input clk,
input reset
);
wire [15:0] YBuffer_0;
reg [15:0] YBuffer_1;
reg [15:0] YBuffer_2;
reg [15:0] YBuffer_3;
reg DValid;
assign YBuffer_0 = input_payload;
assign output_1 = YBuffer_3;
always @(posedge clk or posedge reset) begin
if(reset) begin
YBuffer_1 <= 16'h0;
YBuffer_2 <= 16'h0;
YBuffer_3 <= 16'h0;
DValid <= 1'b0;
end else begin
YBuffer_1 <= YBuffer_0;
YBuffer_2 <= YBuffer_1;
YBuffer_3 <= YBuffer_2;
DValid <= input_valid;
end
end
endmodule
```
### I just changed the Dvalid declaration position,the following source code:
```
case class SerilIIRV2(Qi: Int) extends Component {
val io = new Bundle {
val input = slave(Flow(SInt(Qi bits)))
val output = out(SInt(16 bits))
}
noIoPrefix()
val DValid = Reg(Bool()) init (False)
val YBuffer = History((io.input.payload), 4, DValid, S(0, 16 bits))
DValid := io.input.valid
io.output := YBuffer(3)
}
```
### Generated verilog:
```
`timescale 1ns/1ps
module SerilIIRV2 (
input input_valid,
input [15:0] input_payload,
output [15:0] output_1,
input clk,
input reset
);
reg DValid;
wire [15:0] YBuffer_0;
reg [15:0] YBuffer_1;
reg [15:0] YBuffer_2;
reg [15:0] YBuffer_3;
assign YBuffer_0 = input_payload;
assign output_1 = YBuffer_3;
always @(posedge clk or posedge reset) begin
if(reset) begin
DValid <= 1'b0;
YBuffer_1 <= 16'h0;
YBuffer_2 <= 16'h0;
YBuffer_3 <= 16'h0;
end else begin
if(DValid) begin
YBuffer_1 <= YBuffer_0;
end
if(DValid) begin
YBuffer_2 <= YBuffer_1;
end
if(DValid) begin
YBuffer_3 <= YBuffer_2;
end
DValid <= input_valid;
end
end
endmodule
```
### I don't know why this is happening because the scala syntax isn't used correctly?
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When using History,the following source code:
Generated verilog:
I just changed the Dvalid declaration position,the following source code:
Generated verilog:
I don't know why this is happening because the scala syntax isn't used correctly?
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