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EE6601 - Advanced Wafer Processing

Learning Objective:

• To study deep sub-micron front end process technology.
• To study deep sub-micron back end process technology.
• To study characterization techniques relevant to deep sub-micron process technology.

Comtent:

Dielectrics for CMOS technology. Chemical and mechanical polishing. Lithography and resist technology. Etching process and technology. Backend interconnect technology. Cleaning technology. Process integration. Metrology and analytical techniques.

Learning Outcome:

The students will be exposed to state-of-the-art advanced CMOS process technologies. They will also be exposed to future technology. They will also become more familiar with the relevant diagnostic techniques for process related issues.

Other Relative Information:

• Prior knowledge required: some basic knowledge of MOSFETs and CMOS technology.
• Level of difficulty: medium.
• Mathematics: simple.

Textbooks:

• J. D. Plummer, M. D. Deal, and P. B. Griffin “Silicon VLSI Technology: Fundamentals, Practice, and Modeling,” ISBN-13: 9780130850379, Prentice Hall, 2001.
• C. Y. Chang and S. M. Sze, “ULSI Technology,” ISBN 9780071141055, 1996.

References:

• G. He and Z. Sun, “High-k Gate Dielectrics for CMOS Technology,” ISBN 978-3-527-33032-4-Wiley-VCH, Weinheim, 2012.
• K. Reinhardt and W. Kern, “Handbook of Silicon Wafer Cleaning Technology, 2nd Edition," ISBN-13: 978-0815515548, William Andrew, 2008.
• D. G. Seiler, A. C. Diebold, T. J. Shaffner, R. McDonald, S. Zollner, “Characterization and Metrology for ULSI Technology," International Conference on Characterization and Metrology for ULSI Technology, Austin, Texas, 2003.

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