Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Support for RISC-V GD32VF103 target #236

Draft
wants to merge 1 commit into
base: master
Choose a base branch
from
Draft
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Jump to
Jump to file
Failed to load files.
Diff view
Diff view
1 change: 1 addition & 0 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ include tools/config.mk
WOLFBOOT_ROOT?=$(PWD)
CFLAGS:=-D"__WOLFBOOT"
CFLAGS+=-Werror -Wextra
CFLAGS+=-Wno-array-parameter
LSCRIPT:=config/target.ld
LDFLAGS:=
LD_START_GROUP:=-Wl,--start-group
Expand Down
18 changes: 14 additions & 4 deletions arch.mk
Original file line number Diff line number Diff line change
Expand Up @@ -177,16 +177,26 @@ endif
## RISCV
ifeq ($(ARCH),RISCV)
CROSS_COMPILE:=riscv32-unknown-elf-
CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -g -march=rv32imac -mabi=ilp32 -mcmodel=medany -nostartfiles -DARCH_RISCV
LDFLAGS+=-march=rv32imac -mabi=ilp32 -mcmodel=medany
CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -nostartfiles -DARCH_RISCV
ifeq ($(TARGET),hifive1)
CFLAGS+=-march=rv32imac -mabi=ilp32 -mcmodel=medany
LDFLAGS+=-march=rv32imac -mabi=ilp32 -mcmodel=medany
ARCH_FLASH_OFFSET=0x20010000
OBJS+=src/vector_riscv.o
endif
ifeq ($(TARGET),gd32vf103)
CFLAGS+=-march=rv32imac -mabi=ilp32 -mcmodel=medlow
LDFLAGS+=-march=rv32imac -mabi=ilp32 -mcmodel=medlow
ARCH_FLASH_OFFSET=0x08000000
OBJS+=src/vector_riscv_static.o
endif
MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
OBJS+=src/boot_riscv.o

# Prune unused functions and data
CFLAGS +=-ffunction-sections -fdata-sections
LDFLAGS+=-Wl,--gc-sections

OBJS+=src/boot_riscv.o src/vector_riscv.o
ARCH_FLASH_OFFSET=0x20010000
endif

# powerpc
Expand Down
21 changes: 21 additions & 0 deletions config/examples/gd32v103.config
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
ARCH?=RISCV
TARGET?=gd32vf103
SIGN?=ED25519
HASH?=SHA384
DEBUG?=1
VTOR?=1
CORTEX_M0?=0
NO_ASM?=0
ALLOW_DOWNGRADE?=0
NVM_FLASH_WRITEONCE?=1
WOLFBOOT_VERSION?=1
IMAGE_HEADER_SIZE=512
V?=0
SPMATH?=1
RAM_CODE?=0
DUALBANK_SWAP?=0
WOLFBOOT_PARTITION_SIZE?=0xb800
WOLFBOOT_SECTOR_SIZE?=0x400
WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08007000
WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08013800
WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x0801F000
15 changes: 15 additions & 0 deletions docs/Targets.md
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@ This README describes configuration of supported targets.
* [NXP Kinetis](#nxp-kinetis)
* [NXP T2080 PPC](#nxp-t2080-ppc)
* [SiFive HiFive1 RISC-V](#sifive-hifive1-risc-v)
* [GD32F103 RISC-V](#gd32f103-risc-v)
* [STM32F4](#stm32f4)
* [STM32L4](#stm32l4)
* [STM32F7](#stm32f7)
Expand Down Expand Up @@ -564,6 +565,20 @@ riscv64-unknown-elf-gdb wolfboot.elf -ex "set remotetimeout 240" -ex "target ext
add-symbol-file test-app/image.elf 0x20020100
```

## GD32VF103 RISC-V

This port has been tested on Sipeed Longan nano 1.1.

A configuration file is provided in `config/examples/gd32vf103.config`.

Copy to `.config`, then run `make`.

`factory.bin` can be uploaded by booting the board in DFU mode (keep BOOT button pressed
while rebooting), by running:

`dfu-util -D factory.bin -s 0x08000000 -w`



## STM32F7

Expand Down