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Merge pull request #18 from wolfSSL/stm32wb55
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Added support for STM32WB
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@dgarske
dgarske committed Jul 30, 2019
2 parents ff96298 + 3bd71fa commit 732c82c
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31 changes: 29 additions & 2 deletions docs/Targets.md
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Expand Up @@ -44,7 +44,7 @@ Example 192KB partitioning on STM32-L073
This device is capable of erasing single flash pages (256B each).
However, we choose to use a logic sector size of 4KB for the swaps, to limit the amount of
However, we choose to use a logic sector size of 4KB for the swaps, to limit the amount of
writes to the swap partition.
The proposed geometry in this example `target.h` uses 32KB for wolfBoot, and two
Expand Down Expand Up @@ -88,12 +88,39 @@ Compile with:

`make TARGET=stm32g0 NVM_FLASH_WRITEONCE=1`

## STM32WB55

Example partitioning on Nucleo-68 board:

- Sector size: 4KB
- Wolfboot partition size: 32 KB
- Applicatiobn partition size: 128 KB

```C
#define WOLFBOOT_SECTOR_SIZE 0x1000 /* 4 KB */
#define WOLFBOOT_PARTITION_BOOT_ADDRESS 0x8000
#define WOLFBOOT_PARTITION_SIZE 0x20000 /* 128 KB */
#define WOLFBOOT_PARTITION_UPDATE_ADDRESS 0x28000
#define WOLFBOOT_PARTITION_SWAP_ADDRESS 0x48000
```

### Building

Use `make TARGET=stm32wb`.

The option `NVM_FLASH_WRITEONCE=1` is mandatory on this target, since the IAP driver does not support
multiple writes after each erase operation.

Compile with:

`make TARGET=stm32wb NVM_FLASH_WRITEONCE=1`

## SiFive HiFive1 RISC-V

### Features
* E31 RISC-V 320MHz 32-bit processor
* Onboard 16KB scratchpad RAM
* External 4MB QSPI Flash
* External 4MB QSPI Flash

### Default Linker Settings
* FLASH: Address 0x20000000, Len 0x6a120 (424 KB)
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299 changes: 299 additions & 0 deletions hal/stm32wb.c
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/* stm32wb.c
*
* Copyright (C) 2019 wolfSSL Inc.
*
* This file is part of wolfBoot.
*
* wolfBoot is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* wolfBoot is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/

#include <stdint.h>
#include <image.h>
/* STM32 WB register configuration */

/* Assembly helpers */
#define DMB() __asm__ volatile ("dmb")

/*** RCC ***/

#define RCC_BASE (0x58000000)
#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00))
#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08))
#define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x0C))

#define RCC_CR_PLLRDY (1 << 25)
#define RCC_CR_PLLON (1 << 24)
#define RCC_CR_MSIRDY (1 << 1)
#define RCC_CR_MSION (1 << 0)
#define RCC_CR_HSIRDY (1 << 10)
#define RCC_CR_HSION (1 << 8)
#define RCC_CR_MSIRANGE_SHIFT 4
#define RCC_CR_MSIRANGE_MASK (0x0F << 4)
#define RCC_CR_MSIRANGE_6 (0x06 << 4)

#define RCC_CFGR_SW_MSI 0x0
#define RCC_CFGR_SW_PLL 0x3
#define RCC_CFGR_SW_MASK 0x3

#define RCC_CFGR_HPRE_MASK 0x0F
#define RCC_CFGR_PPRE1_MASK 0x07
#define RCC_CFGR_PPRE2_MASK 0x07
#define RCC_CFGR_HPRE_SHIFT 4
#define RCC_CFGR_PPRE1_SHIFT 8
#define RCC_CFGR_PPRE2_SHIFT 11

#define RCC_PLLCFGR_SRC_SHIFT 0
#define RCC_PLLCFGR_PLLSRC_MSI 0x1
#define RCC_PLLCFGR_PLLSRC_MASK 0x3
#define RCC_PLLCFGR_PLLM_DIV2 (0x1 << 4)
#define RCC_PLLCFGR_PLLM_MASK (0x3 << 4)
#define RCC_PLLCFGR_PLLN_32 (32 << 8)
#define RCC_PLLCFGR_PLLN_MASK (0x7f << 8)
#define RCC_PLLCFGR_PLLP_DIV5 (4 << 17)
#define RCC_PLLCFGR_PLLP_MASK (0x7 << 17)
#define RCC_PLLCFGR_PLLQ_DIV4 (3 << 25)
#define RCC_PLLCFGR_PLLQ_MASK (0x7 << 25)
#define RCC_PLLCFGR_PLLR_DIV2 (1 << 29)
#define RCC_PLLCFGR_PLLR_MASK (0x7 << 29)
#define RCC_PLLCFGR_PLLP_EN (1 << 16)
#define RCC_PLLCFGR_PLLQ_EN (1 << 24)
#define RCC_PLLCFGR_PLLR_EN (1 << 28)

#define RCC_PRESCALER_DIV_NONE 0


/*** FLASH ***/
#define FLASH_BASE (0x58004000)
#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
#define FLASH_KEY (*(volatile uint32_t *)(FLASH_BASE + 0x08))
#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x10))
#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x14))

#define FLASHMEM_ADDRESS_SPACE (0x08000000)
#define FLASH_PAGE_SIZE (0x1000) /* 4KB */

/* Register values */
#define FLASH_ACR_LATENCY_MASK (0x07)

#define FLASH_SR_BSY (1 << 16)
#define FLASH_SR_SIZERR (1 << 6)
#define FLASH_SR_PGAERR (1 << 5)
#define FLASH_SR_WRPERR (1 << 4)
#define FLASH_SR_PROGERR (1 << 3)
#define FLASH_SR_EOP (1 << 0)

#define FLASH_CR_LOCK (1 << 31)
#define FLASH_CR_STRT (1 << 16)

#define FLASH_CR_PER (1 << 1)
#define FLASH_CR_PG (1 << 0)

#define FLASH_CR_PNB_SHIFT 3
#define FLASH_CR_PNB_MASK 0x3f

#define FLASH_KEY1 (0x45670123)
#define FLASH_KEY2 (0xCDEF89AB)


static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
{
uint32_t reg = FLASH_ACR;
if ((reg & FLASH_ACR_LATENCY_MASK) != waitstates)
FLASH_ACR |= ((reg & ~FLASH_ACR_LATENCY_MASK) | waitstates);
}

static RAMFUNCTION void flash_wait_complete(void)
{
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
}

static void RAMFUNCTION flash_clear_errors(void)
{
FLASH_SR |= ( FLASH_SR_SIZERR | FLASH_SR_PGAERR | FLASH_SR_WRPERR | FLASH_SR_PROGERR);
}

int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
{
int i = 0;
uint32_t *src, *dst;
flash_clear_errors();
FLASH_CR |= FLASH_CR_PG;

while (i < len) {
flash_clear_errors();
if ((len - i > 3) && ((((address + i) & 0x07) == 0) && ((((uint32_t)data) + i) & 0x07) == 0)) {
src = (uint32_t *)data;
dst = (uint32_t *)(address + FLASHMEM_ADDRESS_SPACE);
flash_wait_complete();
dst[i >> 2] = src[i >> 2];
dst[(i >> 2) + 1] = src[(i >> 2) + 1];
flash_wait_complete();
i+=8;
} else {
uint32_t val[2];
uint8_t *vbytes = (uint8_t *)(val);
int off = (address + i) - (((address + i) >> 3) << 3);
uint32_t base_addr = address & (~0x07); /* aligned to 64 bit */
int u32_idx = (i >> 2);
dst = (uint32_t *)(base_addr);
val[0] = dst[u32_idx];
val[1] = dst[u32_idx + 1];
while ((off < 8) && (i < len))
vbytes[off++] = data[i++];
dst[u32_idx] = val[0];
dst[u32_idx + 1] = val[1];
flash_wait_complete();
}
}
if ((FLASH_SR & FLASH_SR_EOP) == FLASH_SR_EOP)
FLASH_SR |= FLASH_SR_EOP;
FLASH_CR &= ~FLASH_CR_PG;
return 0;
}

void RAMFUNCTION hal_flash_unlock(void)
{
flash_wait_complete();
if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
FLASH_KEY = FLASH_KEY1;
DMB();
FLASH_KEY = FLASH_KEY2;
DMB();
while ((FLASH_CR & FLASH_CR_LOCK) != 0)
;
}
}

void RAMFUNCTION hal_flash_lock(void)
{
flash_wait_complete();
if ((FLASH_CR & FLASH_CR_LOCK) == 0)
FLASH_CR |= FLASH_CR_LOCK;
}


int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
{
int start = -1, end = -1;
uint32_t end_address;
uint32_t p;
if (len == 0)
return -1;
end_address = address + len - 1;
for (p = address; p < end_address; p += FLASH_PAGE_SIZE) {
uint32_t reg = FLASH_CR & (~(FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT));
FLASH_CR = reg | ((p >> 12) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER | FLASH_CR_PG;
DMB();
FLASH_CR |= FLASH_CR_STRT;
flash_wait_complete();
FLASH_CR &= ~(FLASH_CR_PER | FLASH_CR_PG);
}
return 0;
}

static void clock_pll_off(void)
{
uint32_t reg32;
/* Enable internal high-speed oscillator. */
RCC_CR |= RCC_CR_MSION;
DMB();
while ((RCC_CFGR & RCC_CR_MSIRDY) == 0) {};
/* Select MSI as SYSCLK source. */
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_SW_MASK);
DMB();
/* Turn off PLL */
RCC_CR &= ~RCC_CR_PLLON;
DMB();
}

static void clock_pll_on(void)
{
uint32_t reg32;
uint32_t cpu_freq, pllm, plln, pllp,pllq, pllr;
uint32_t hpre, ppre1, ppre2;
uint32_t flash_waitstates;

/* Select clock parameters (CPU Speed = 64MHz) */
cpu_freq = 64000000;
flash_waitstates = 4;
flash_set_waitstates(flash_waitstates);

/* Configure + enable internal high-speed oscillator. */
RCC_CR = (RCC_CR & (~RCC_CR_MSIRANGE_MASK)) | RCC_CR_MSIRANGE_6;
RCC_CR |= RCC_CR_MSION;
DMB();
while ((RCC_CR & RCC_CR_MSIRDY) == 0)
;
/* Select MSI as SYSCLK source. */
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_SW_MASK);
RCC_CFGR = (reg32 | RCC_CFGR_SW_MSI);
DMB();
/*
* Set prescalers
*/
hpre = RCC_PRESCALER_DIV_NONE;
ppre1 = RCC_PRESCALER_DIV_NONE;
ppre2 = RCC_PRESCALER_DIV_NONE;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
RCC_CFGR = (hpre & RCC_CFGR_HPRE_MASK) << RCC_CFGR_HPRE_SHIFT;
DMB();
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
DMB();
reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
DMB();
/* Set PLLCFGR parameter */
RCC_PLLCFGR = RCC_PLLCFGR_PLLM_DIV2 | RCC_PLLCFGR_PLLN_32 |
RCC_PLLCFGR_PLLP_DIV5 | RCC_PLLCFGR_PLLQ_DIV4 |
RCC_PLLCFGR_PLLR_DIV2 | RCC_PLLCFGR_PLLP_EN |
RCC_PLLCFGR_PLLQ_EN | RCC_PLLCFGR_PLLR_EN |
RCC_PLLCFGR_PLLSRC_MSI;

/* Enable PLL oscillator and wait for it to stabilize. */
RCC_CR |= RCC_CR_PLLON;
DMB();
while ((RCC_CR & RCC_CR_PLLRDY) == 0)
;

/* Select PLL as SYSCLK source. */
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_SW_MASK);
RCC_CFGR = (reg32 | RCC_CFGR_SW_PLL);
DMB();
/* Wait for PLL clock to be selected (via SWS, bits 3:2) */
while (((RCC_CFGR >> 2) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL)
;
}

void hal_init(void)
{
clock_pll_on();
}

void hal_prepare_boot(void)
{
#ifdef SPI_FLASH
spi_release();
#endif
hal_flash_lock();
clock_pll_off();
}

44 changes: 44 additions & 0 deletions hal/stm32wb.ld
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MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x8000
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
}

SECTIONS
{
.text :
{
_start_text = .;
KEEP(*(.isr_vector))
*(.text*)
*(.rodata*)
. = ALIGN(4);
_end_text = .;
} > FLASH

_stored_data = .;
.data : AT (_stored_data)
{
_start_data = .;
KEEP(*(.data*))
. = ALIGN(4);
KEEP(*(.ramcode))
. = ALIGN(4);
_end_data = .;
} > RAM

.bss (NOLOAD) :
{
_start_bss = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
_end_bss = .;
__bss_end__ = .;
_end = .;
} > RAM
. = ALIGN(4);
}

END_STACK = ORIGIN(RAM) + LENGTH(RAM);

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