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i, r, ld, s, b type instructions(no counters)

i, r, ld, s, b type instructions(no counters)

 
 

i, r, ld, s, b, uj type instructions(using counters)

i, r, ld, s, b, uj type instructions(using counters)

 
 

i_type and r_type together

i_type and r_type together

 
 

i_type instructions

i_type instructions

 
 

i_type, r_type(including ^, |, &, <<, >>, >>>), load and store instructions(no counters)

i_type, r_type(including ^, |, &, <<, >>, >>>), load and store instructions(no counters)

 
 

i_type, r_type(including ^, |, &, <<, >>, >>>), load and store instructions(using counters)

i_type, r_type(including ^, |, &, <<, >>, >>>), load and store instructions(using counters)

 
 

r_type instructions

r_type instructions

 
 

.DS_Store

.DS_Store

 
 

LICENSE

LICENSE

 
 

README.md

README.md

 
 

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RISC-V-architecture-design

#designing RISC-V architecture using Verilog HDL in XILINX VIVADO PC SUITE #each folder contains corresponding source files, input and output files, and screenshots of simulations

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designing RISC-V architecture using Verilog HDL in XILINX VIVADO PC SUITE

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datapath verilog-hdl xilinx-vivado riscv64 controlpath risc-varchitecture hennessy-and-patterson

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