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This is v10.2 release commit
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vhelin committed Jun 24, 2022
1 parent 22364dd commit f1af0f6
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6 changes: 3 additions & 3 deletions CHANGELOG
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1... WLA GB-Z80/Z80/6502/65C02/65CE02/65816/6800/6801/6809/8008/8080/HUC6280/SPC-700/SuperFX History
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v10.2 (20-Jun-2022) [ALL] Added SIZE to .RAMSECTION.
v10.2 (24-Jun-2022) [ALL] Added SIZE to .RAMSECTION.
[ALL] Added -d to disable WLA's ability to calculate A-B
where A and B are labels.
[ALL] If SIZE is used with a .SECTION or .RAMSECTION and
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------------------------------------------------------------------------------


v5.17 (05-Jun-2022) Added SIZE to [sections] and [ramsections].
v5.17 (24-Jun-2022) Added SIZE to [sections] and [ramsections].
Added -R (file paths inside link file are relative to
linkfile's location).
WLALINK's summary is now printed to stdout instead of
Expand All @@ -1407,7 +1407,7 @@ v5.17 (05-Jun-2022) Added SIZE to [sections] and [ramsections].
We now skip the generated RAM_USAGE_SLOT_* labels when
trying to automatically find load address for a CBMPRG.

v5.16 (19-Feb-2021) Added support for WINDOW and BITWINDOW in .SECTION and
v5.16 (19-Feb-2022) Added support for WINDOW and BITWINDOW in .SECTION and
.RAMSECTION.
Fixed multiple memory leaks. Should now work better
on an Amiga.
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2 changes: 1 addition & 1 deletion README.md
Expand Up @@ -20,7 +20,7 @@ memory map (that should be shared across all object and library files).
Supported architectures are:

* Z80
* GB (Z80-GB)
* GB (GB-Z80)
* 6502
* 65C02
* 65CE02
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4 changes: 2 additions & 2 deletions doc/conf.py
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#source_encoding = 'utf-8-sig'
master_doc = 'wla-dx'
project = u'wla-dx'
copyright = u'2021, vhelin'
copyright = u'1998, vhelin'
version = '10.2' # The short X.Y version, can be used with |version|
release = '10.2a' # The full version, including alpha/beta/rc tags, |release|
release = '10.2' # The full version, including alpha/beta/rc tags, |release|
language = None
#today = ''
#today_fmt = '%B %d, %Y'
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