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40: Extend stackmap format to allow for derived types. r=ltratt a=vext01



Co-authored-by: Edd Barrett <vext01@gmail.com>
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bors[bot] and vext01 committed Aug 18, 2022
2 parents 9a27a07 + 5c1340d commit 22e35b8
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Showing 60 changed files with 1,674 additions and 661 deletions.
19 changes: 11 additions & 8 deletions llvm/docs/StackMaps.rst
View file
Expand Up @@ -338,14 +338,17 @@ format of this section follows:
uint64 : PatchPoint ID
uint32 : Instruction Offset
uint16 : Reserved (record flags)
uint16 : NumLocations
Location[NumLocations] {
uint8 : Register | Direct | Indirect | Constant | ConstantIndex
uint8 : Reserved (expected to be 0)
uint16 : Location Size
uint16 : Dwarf RegNum
uint16 : Reserved (expected to be 0)
int32 : Offset or SmallConstant
uint16 : NumLiveVars
LiveVars[NumLiveVars] {
uint8 : NumLocations
Locations[NumLocations] {
uint8 : Register | Direct | Indirect | Constant | ConstantIndex
uint8 : Reserved (expected to be 0)
uint16 : Location Size
uint16 : Dwarf RegNum
uint16 : Reserved (expected to be 0)
int32 : Offset or SmallConstant
}
}
uint32 : Padding (only if required to align to 8 byte)
uint16 : Padding
Expand Down
200 changes: 113 additions & 87 deletions llvm/include/llvm/CodeGen/StackMaps.h
View file
Expand Up @@ -59,87 +59,6 @@ class StackMapOpers {
}
};

/// MI-level patchpoint operands.
///
/// MI patchpoint operations take the form:
/// [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
///
/// IR patchpoint intrinsics do not have the <cc> operand because calling
/// convention is part of the subclass data.
///
/// SD patchpoint nodes do not have a def operand because it is part of the
/// SDValue.
///
/// Patchpoints following the anyregcc convention are handled specially. For
/// these, the stack map also records the location of the return value and
/// arguments.
class PatchPointOpers {
public:
/// Enumerate the meta operands.
enum { IDPos, NBytesPos, TargetPos, NArgPos, CCPos, MetaEnd };

private:
const MachineInstr *MI;
bool HasDef;

unsigned getMetaIdx(unsigned Pos = 0) const {
assert(Pos < MetaEnd && "Meta operand index out of range.");
return (HasDef ? 1 : 0) + Pos;
}

const MachineOperand &getMetaOper(unsigned Pos) const {
return MI->getOperand(getMetaIdx(Pos));
}

public:
explicit PatchPointOpers(const MachineInstr *MI);

bool isAnyReg() const { return (getCallingConv() == CallingConv::AnyReg); }
bool hasDef() const { return HasDef; }

/// Return the ID for the given patchpoint.
uint64_t getID() const { return getMetaOper(IDPos).getImm(); }

/// Return the number of patchable bytes the given patchpoint should emit.
uint32_t getNumPatchBytes() const {
return getMetaOper(NBytesPos).getImm();
}

/// Returns the target of the underlying call.
const MachineOperand &getCallTarget() const {
return getMetaOper(TargetPos);
}

/// Returns the calling convention
CallingConv::ID getCallingConv() const {
return getMetaOper(CCPos).getImm();
}

unsigned getArgIdx() const { return getMetaIdx() + MetaEnd; }

/// Return the number of call arguments
uint32_t getNumCallArgs() const {
return MI->getOperand(getMetaIdx(NArgPos)).getImm();
}

/// Get the operand index of the variable list of non-argument operands.
/// These hold the "live state".
unsigned getVarIdx() const {
return getMetaIdx() + MetaEnd + getNumCallArgs();
}

/// Get the index at which stack map locations will be recorded.
/// Arguments are not recorded unless the anyregcc convention is used.
unsigned getStackMapStartIdx() const {
if (isAnyReg())
return getArgIdx();
return getVarIdx();
}

/// Get the next scratch register operand index.
unsigned getNextScratchIdx(unsigned StartIdx = 0) const;
};

/// MI-level Statepoint operands
///
/// Statepoint operands take the form:
Expand Down Expand Up @@ -231,6 +150,11 @@ class StatepointOpers {
/// Get index of number of gc allocas.
unsigned getNumAllocaIdx();

/// Return the index after skipping `NumVars` live variables, starting from
/// `StartIdx`.
unsigned skipLiveVars(const MachineInstr *MI, unsigned StartIdx,
unsigned NumVars);

/// Get index of number of GC pointers.
unsigned getNumGCPtrIdx();

Expand Down Expand Up @@ -283,21 +207,34 @@ class StackMaps {
// OpTypes are used to encode information about the following logical
// operand (which may consist of several MachineOperands) for the
// OpParser.
using OpType = enum { DirectMemRefOp, IndirectMemRefOp, ConstantOp };
using OpType = enum {
DirectMemRefOp,
IndirectMemRefOp,
ConstantOp,
NextLive
};

StackMaps(AsmPrinter &AP);

/// Get index of next meta operand.
/// Similar to parseOperand, but does not actually parses operand meaning.
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx);

static bool isNextLive(MachineOperand &MO) {
return isNextLive(const_cast<const MachineOperand &>(MO));
}
static bool isNextLive(const MachineOperand &MO) {
return MO.isImm() && (MO.getImm() == NextLive);
}

void reset() {
CSInfos.clear();
ConstPool.clear();
FnInfos.clear();
}

using LocationVec = SmallVector<Location, 8>;
using LiveVarsVec = SmallVector<LocationVec, 8>;
using LiveOutVec = SmallVector<LiveOutReg, 8>;
using ConstantPool = MapVector<uint64_t, uint64_t>;

Expand All @@ -312,13 +249,13 @@ class StackMaps {
struct CallsiteInfo {
const MCExpr *CSOffsetExpr = nullptr;
uint64_t ID = 0;
LocationVec Locations;
LiveVarsVec LiveVars;
LiveOutVec LiveOuts;

CallsiteInfo() = default;
CallsiteInfo(const MCExpr *CSOffsetExpr, uint64_t ID,
LocationVec &&Locations, LiveOutVec &&LiveOuts)
: CSOffsetExpr(CSOffsetExpr), ID(ID), Locations(std::move(Locations)),
LiveVarsVec &&LiveVars, LiveOutVec &&LiveOuts)
: CSOffsetExpr(CSOffsetExpr), ID(ID), LiveVars(std::move(LiveVars)),
LiveOuts(std::move(LiveOuts)) {}
};

Expand Down Expand Up @@ -360,15 +297,15 @@ class StackMaps {

MachineInstr::const_mop_iterator
parseOperand(MachineInstr::const_mop_iterator MOI,
MachineInstr::const_mop_iterator MOE, LocationVec &Locs,
MachineInstr::const_mop_iterator MOE, LiveVarsVec &LiveVars,
LiveOutVec &LiveOuts) const;

/// Specialized parser of statepoint operands.
/// They do not directly correspond to StackMap record entries.
void parseStatepointOpers(const MachineInstr &MI,
MachineInstr::const_mop_iterator MOI,
MachineInstr::const_mop_iterator MOE,
LocationVec &Locations, LiveOutVec &LiveOuts);
LiveVarsVec &LiveVars, LiveOutVec &LiveOuts);

/// Create a live-out register record for the given register @p Reg.
LiveOutReg createLiveOutReg(unsigned Reg,
Expand Down Expand Up @@ -407,6 +344,95 @@ class StackMaps {
void debug() { print(dbgs()); }
};

/// MI-level patchpoint operands.
///
/// MI patchpoint operations take the form:
/// [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
///
/// IR patchpoint intrinsics do not have the <cc> operand because calling
/// convention is part of the subclass data.
///
/// SD patchpoint nodes do not have a def operand because it is part of the
/// SDValue.
///
/// Patchpoints following the anyregcc convention are handled specially. For
/// these, the stack map also records the location of the return value and
/// arguments.
class PatchPointOpers {
public:
/// Enumerate the meta operands.
enum { IDPos, NBytesPos, TargetPos, NArgPos, CCPos, MetaEnd };

private:
const MachineInstr *MI;
bool HasDef;

unsigned getMetaIdx(unsigned Pos = 0) const {
assert(Pos < MetaEnd && "Meta operand index out of range.");
return (HasDef ? 1 : 0) + Pos;
}

const MachineOperand &getMetaOper(unsigned Pos) const {
return MI->getOperand(getMetaIdx(Pos));
}

public:
explicit PatchPointOpers(const MachineInstr *MI);

bool isAnyReg() const { return (getCallingConv() == CallingConv::AnyReg); }
bool hasDef() const { return HasDef; }

/// Return the ID for the given patchpoint.
uint64_t getID() const { return getMetaOper(IDPos).getImm(); }

/// Return the number of patchable bytes the given patchpoint should emit.
uint32_t getNumPatchBytes() const { return getMetaOper(NBytesPos).getImm(); }

/// Returns the target of the underlying call.
const MachineOperand &getCallTarget() const { return getMetaOper(TargetPos); }

/// Returns the calling convention
CallingConv::ID getCallingConv() const { return getMetaOper(CCPos).getImm(); }

unsigned getArgIdx() const { return getMetaIdx() + MetaEnd; }

/// Return the number of call arguments
uint32_t getNumCallArgs() const {
return MI->getOperand(getMetaIdx(NArgPos)).getImm();
}

/// Get the operand index of the variable list of non-argument operands.
/// These hold the "live state".
unsigned getVarIdx() const {
if (!isAnyReg())
return getMetaIdx() + MetaEnd + getNumCallArgs();

// For anyregcc, the args go into the stackmap section and thus each
// arguments isn't necessarily of fixed sized. We will have to scan until
// we have seen enough NextLive markers.
unsigned Idx = getMetaIdx() + MetaEnd;
unsigned Remain = getNumCallArgs();
while (Remain) {
MachineOperand MO = MI->getOperand(Idx);
if (StackMaps::isNextLive(MO))
Remain--;
Idx = StackMaps::getNextMetaArgIdx(MI, Idx);
}
return Idx;
}

/// Get the index at which stack map locations will be recorded.
/// Arguments are not recorded unless the anyregcc convention is used.
unsigned getStackMapStartIdx() const {
if (isAnyReg())
return getArgIdx();
return getVarIdx();
}

/// Get the next scratch register operand index.
unsigned getNextScratchIdx(unsigned StartIdx = 0) const;
};

} // end namespace llvm

#endif // LLVM_CODEGEN_STACKMAPS_H

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