[Question] How to use case statement with don't care?

[nananapo]

Hi.
Is the case statement with don't care like casez or casex supported?
I want to use it to implement a decoder.

[taichi-ishitani]

Veryl has not yet supported these statement.

@dalance
SystemVerilog has case inside statement that is enhanced version of casex statement.
So I think Veryl should support case inside but has not to support casex and casez statements.

[nananapo]

By the way, case expression seems to be converted into logic using ternary operator ?. But I think converting into case statement is better.

[dalance]

By the way, case expression seems to be converted into logic using ternary operator ?. But I think converting into case statement is better.

The reason using ternary operator is that it can be used at arbitrary expression context like below:

// pass
localparam A = X == 1 ? 0 : 1;

// fail
localparam A = case (X)
    1: 0;
    default: 1;
endcase

[nananapo]

I think it would be nice if the semantics of case expression and statement are not different.

[taichi-ishitani]

SystemVerilog does not have if expression and case expression features so I think it's difficult.