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[Feature] case inside
statement and expression
#643
Comments
Emitting From case x {
0 : a = 1,
1..3 : a = 2,
'h1xx : a = 3,
default: a = 4,
} To case (x) inside {
0 : a = 1,
[1:2] : a = 2,
'h1xx : a = 3,
default: a = 4,
} |
Like the exmaple below, behavior of case (a)
b: c = 1; // select only when a == b
default c = 0;
endcase
case (a) inside
b: c = 1; // select when a == b or b is unknown
default c = 0;
endcase So I think these should be different syntax. |
This behavior may cause difference between simulation and synthesis result. I think it can be solution for this problem to introduce limitation that |
I think the following
case a {
0 : c = 1;
default: c = 2;
}
switch {
a == b : c = 1;
default: c = 2;
} case (a) inside
0: c = 1;
default: c = 2;
endcase
case (1)
a == b : c = 1;
default: c = 2;
endcase |
SystemVerilog has the
case inside
statement that is enhanced version ofcasex
statetment.Veryl should support it.
Originally posted by @taichi-ishitani in #641 (comment)
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