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Bug fix: asymmetric grid with bidirectional routing #2514

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ThomasJagielski
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Replace grid.width() check with grid.height() for top perimeter channels

Description

For FPGA fabrics with non-square grids and bidirectional routing the check to determine if you were on a perimeter tile was incorrect. The check compared the (x,y) location against the grid.width() for both dimensions. The vertical dimension should be compared against the grid.height().

Related Issue

Motivation and Context

Before this change, asymmetric grid dimensions with bidirectional routing would result in a "node_index" assertion error and a "core dump" which aborted vpr execution while creating the routing resource graph. This change will now allow you to run vpr on non-square grids with bidirectional routing.

How Has This Been Tested?

All regression tests were rerun and passed locally. A simple example with an asymmetric grid and bidirectional routing that previously resulted in a core dump and node_index assertion error was also run through the vpr flow successfully on my local machine.

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

Replace grid.width() check with grid.height() for top perimeter channels
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Mar 21, 2024
@vaughnbetz
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Thanks! Will merge once CI passes.

@vaughnbetz vaughnbetz merged commit 7ed749f into verilog-to-routing:master May 29, 2024
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2 participants