Updating k6_N10_40nm.xml arch and adding a sparse version; making more user friendly for teaching use #2454
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Updating k6_N10_40nm.xml and adding k6_N10_sparse_crossbar_40nm.xml. These architectures are now more heavily commented and suitable for work in a grad course (ECE 1756).
Description
I cut the logic block areas to something more reasonable for a simple architecture like this; the area numbers for the logic blocks and the local mux delays for the sparse architecture are based on coarse scaling / guessing so they aren't extremely accurate.
Removed some very complex comments, and added some more basic ones. Deleted dead code and comments in the arch files. Switched to per LUT input delays so we can demonstrate flat routing.
Motivation and Context
Useful for teaching (assignment 4) in ECE 1756.
How Has This Been Tested?
Tested with simple MCNC designs to show they work and get reasonable results.
Checklist: