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Global Nets Routing constraints #2446
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…ent type is part of the general routing or clock network
…ute added to the segment tag
…dded to the segment tag
…node for clock network
…onflicts with one of the values of operation_list in odin_types.h
… to identify the name of the clock network the node belongs to
…ting to be skipped
…pe for rr_nodes and res_type for rr_segments
…pe for rr_nodes and res_type for rr_segments
… and modify VPR constraints class to contain instances of placement and route constraints
…straints file before calling the route flow - Updates in Tulong4Dev:route_constraint_dev branch have been used as a baseline for these changes
… - Updates in Tulong4Dev:route_constraint_dev branch have been used as a baseline for these changes
…ual sink of the clock network
…ugh getter functions defined in user constraints class
…aints - removed accidentally during resoloving of merge conflict
…r of the t_arch struct
…o global routing constraints and placement constraints
…escription documentation
@kimiatkh : a gentle nag to update this so we can try to land it. |
@duck2 : Kimia has had to add some special code (a very small amount) to deal with the virtual sinks for clock routing on dedicate clock networks. For such sinks, she passes -1 as the target_net_pin_index, and does not mark it in the _is_isink_reached array (since there is no sink index to mark as the pre-routed part of the net to get to the dedicated clock network drive point does not correspond to any one connection). Does anything else have to happen to make this work with the parallel router and/or net decomposition? E.g. should clock networks always be routed in the root partition and/or never be decomposed so we don't have to worry about them? Or should everything work without change? @kimiatkh : I think you'll have to test with parallel routing on too, and make regtests that combine parallel routing on with dedicated_clock_network routing on. |
kimia did a quick test on a small circuit with parallel code (a January version) and it worked with dedicated clock routing. It may not be a strong enough test though, as perhaps there are no nets that can be routed in parallel in such a small device. |
@kimiatkh : please remove the spurious error messages that the rrgraph node count doesn't match the expected (as the comment says this will happen every time with dedicate clock networks!). |
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Looks good!
@@ -1975,6 +1975,10 @@ The ``<segment>`` tag and its contents are described below. | |||
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.. note:: ``longline`` is only supported on with ``bidir`` routing | |||
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:opt_param res_type: | |||
Specifies whether the segment belongs to the general or a clock routing network. If this tag is not specified, the resource type for | |||
the segment is considered to be GENERAL. |
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I'd add at the end "(i.e. regular routing)."
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.. option:: --write_vpr_constraints <file> | ||
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Writes out new :ref:`floorplanning constraints <vpr_constraints_file>` based on current placement to the specified XML file. | ||
Writes out new :ref:`floorplanning constraints <placement_constraints>` based on current placement to the specified XML file. |
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"based on the current placement" (add a "the")
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Distinguishing Between Clock Networks | ||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
Given the support for multiple clock networks, VPR needs a way to distinguish between different virtual sinks belonging to various clock networks. This is achieved through the optional ``"name"`` attribute for the rr_node, accepting a string used as the clock network name. Therefore, when the ``"clk_res_type"`` is set to ``"VIRTUAL_SINK"``, the attribute ``"name"`` becomes a requried parameter to enable VPR to determine which clock netwrok the virtual sink belongs to. |
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netwrok --> typo
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
The node types ``"CHANX"`` and ``"CHANY"`` can construct the clock routing architecture, similar to a generic routing network. However, to identify nodes that are part of a clock network, one can define unique segments for clock networks. To indicate that a segment defined is a clock network resource, users can use the optional attribute ``res_type="GCLK"``. Therefore, nodes with a segment ID of this defined segment are considered to be part of a clock network. | ||
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While VPR currently does not leverage this distinction of clock network resources, it is recommended to use the ``res_type="GCLK"`` attribute, as this preparation ensures compatibility for future support. |
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It would be good to add an example of clock network routing here. You'd give little snippets of each file that together would make sense.
I think clock nets don't get decomposed anyway, so this should be OK if it works with |
@kimiatkh : it would be good to land this. I have just a few comments to address, plus there is a conflict to resolve. CI passed, so once those are handled I think this can be merged. |
This branch introduces support for designating any net as global by utilizing a VPR constraints XML file, enabling users to define the routing method for each global net.
Here is an example of routing constraints defined within vpr_constraints:
In this example:
The name attribute supports wildcard patterns for flexible net matching.
The route_model attribute can be set to "ideal," "route," or "dedicated_network." Refer to the documentation here for details.
When route_model is set to "dedicated_network," the user must also specify the name of the dedicated network through the network_name attribute.
Additionally, this branch introduces support for identifying clock-related resources in the rr graph. Clock segments are now identified using the optional attribute res_type set to "gclk." To pinpoint virtual sink nodes specific to clock networks, a new optional attribute clk_res_type is introduced within the rr node tags, currently supporting "virtual_sink." The variable name is introduced to accommodate multiple clock networks, referencing the clock network's name when clk_res_type is set to "virtual_sink."
Motivation and Context:
With modern FPGAs incorporating dedicated clock networks, often spanning multiple clock regions, VPR's existing support for modeling and routing through such networks is limited. This pull request addresses this limitation by enhancing VPR's understanding of clock network resources and adding support to specify the routing methods for global nets through a constraints file.
Types of changes
[ ] Bug fix (change which fixes an issue)
[x]New feature (change which adds functionality)
[ ]Breaking change (fix or feature that would cause existing functionality to change)
Checklist:
My change requires a change to the documentation
[x] I have updated the documentation accordingly
[x] I have added tests to cover my changes
[ ] All new and existing tests passed