Segment fault

[narutozxp]

It seems that grid_layouts.size() is always larger than 1, even if my architecture has just one layer. Therefore, the following code will result in segment fault.

vtr-verilog-to-routing/libs/libarchfpga/src/echo_arch.cpp

Lines 234 to 238 in 17a816a

	fprintf(Echo, "\tInput Connect Block Switch Name Within a Same Die: %s\n", arch->ipin_cblock_switch_name[0].c_str());
	//if there is more than one layer available, print the connection block switch name that is used for connection between two dice
	if (arch->grid_layouts.size() > 1) {
	fprintf(Echo, "\tInput Connect Block Switch Name Between Two Dice: %s\n", arch->ipin_cblock_switch_name[1].c_str());
	}