GitHub - ufukkaraca/Verilog_AES256: Verilog implementation of the Advanced Encryption Standard.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commits
README.txt		README.txt
anaModul.v		anaModul.v
bitDegistirme.v		bitDegistirme.v
keyExpansion.v		keyExpansion.v
rconExchange.v		rconExchange.v
rijndaelSBox.v		rijndaelSBox.v
satirKaydirma.v		satirKaydirma.v
sutunKaristirma.v		sutunKaristirma.v
yurutucuModul.v		yurutucuModul.v

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These scripts were created as part of a logic circuit design project and some subscripts may not be fully functional as this project was co-developed by different contributers.