zynq
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Parallella RISC-V Prebuilt Images
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Aug 18, 2016
Logisim and VHDL Files for an alarm_clock that was realized on a development board at University
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Mar 21, 2017 - VHDL
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
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Mar 24, 2017 - VHDL
Full Search Motion Estimation Accelerator IP
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Jun 6, 2017 - VHDL
mirror of https://git.elphel.com/Elphel/eddr3
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Oct 16, 2017 - Verilog
localization of sound source by cross-correlating three ΣΔ-modulated microphone signals in a zynq FPGA SoC
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Jan 11, 2018 - C++
Using Vivado HLS to create floating point IP, used to accelerate a Zynq system. Multiple engines are instantiated.
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Jan 21, 2018 - VHDL
UltraZed Development
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Mar 16, 2018 - C
EE 175 Senior Design. Multibaseline Stereo Camera
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Mar 17, 2018 - C
📻 Using Software Designed Radio to transmit & receive FM signal
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Apr 2, 2018 - MATLAB
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