EC302-VLSI-Design-Lab
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Updated
Nov 2, 2022 - Roff
EC302-VLSI-Design-Lab
Layout Description Framework, a framework to help semi-custom or full-custom designers create the layout of their ICs by writing C# code.
The VLSI problem requires to fit all the rectangles in the grid without overlapping one on an another, by minimizing the height of the grid.
This is a RISC-like implementation for a 5-stages pipelined processor implemented with Verilog which follows Harvard architecture with 2 separated memories one for the data and the other for the instructions.
In this project, I conducted an in-depth comparative analysis of various adder architectures to assess their performance in terms of delay and power consumption.
This is the repo for the project in Combinatorial and Decision Making Optimization (Module 1)
This repository contains a CMOS inverter circuit designed and simulated using LTspice. A CMOS inverter which is actually a "Hello World" in VLSI design logic is a fundamental building block in digital electronics, and this project aims to showcase its operation and characteristics.
EC704 - VLSI Design Automation
Using a pulse wave as an input referencing as clock we try to generate three different pulses having different pulse width
Projects done by Reet
digital and analog cosimulation for ACT and Xyce
This repository contains code files for VLSI Laboratory - EC39004, conducted in Spring 2024 at IIT Kharagpur
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