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15 public repositories
matching this topic...
Examples of Halide language algorithms running on RISC-V
Updated
Feb 9, 2024
Assembly
Patched version of LLVM to unblock RISC-V vectorization with 0.7.1 ISA
RISCV Vector Kernel C/LLVM-IR generator
Examples of Halide language algorithms running on RISC-V
Updated
Mar 1, 2023
Assembly
MagicMirror² module: Departure monitor for the RVV (Regensburger Verkehrsverbund) bus system (ÖPNV, public transport)
Updated
Jan 21, 2021
JavaScript
Updated
Jan 9, 2021
Scala
Hair recoloring on RISC-V with OpenCV
Updated
Apr 19, 2023
Python
A translator from ARM NEON intrinsics to RISCV-V Extension implementation
x86-64, ARM, and RVV intrinsics viewer
Updated
May 19, 2024
JavaScript
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
Updated
May 30, 2024
HTML
Implements kernels with RISC-V Vector
Updated
Mar 24, 2023
Assembly
Unit tests generator for RVV 1.0
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
Updated
May 26, 2024
Assembly
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
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