risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
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NCKU Computer Organization 2023
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Aug 11, 2023 - C
🛠️ Docker image with QEMU configured for RISC-V emulation. Perfectly suited for cross-debugging RISC-V.
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Sep 10, 2023 - Dockerfile
hello world in bare-metal rust / risc-v.
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Aug 26, 2023 - Rust
The WIOM: A RV32IM In-Order pipelined cpu with no cache and a naive branch predictor.
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Jun 23, 2023 - C
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Jul 11, 2017 - Go
This is a project repository for Maham and Shiza Computer Architecture
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Apr 30, 2019
riscv_myth_workshop created by GitHub Classroom. Contains an implemented RISC-V 32-bit core.
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Oct 26, 2020 - Coq