Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
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Updated
Jul 28, 2023 - Verilog
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
SystemRDL 2.0 language compiler front-end
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Generate UVM register model from compiled SystemRDL input
Control and status register code generator toolchain
Generate address space documentation HTML from compiled SystemRDL input
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