AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Updated
May 22, 2024 - SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Network on Chip Implementation written in SytemVerilog
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
A Chisel RTL generator for network-on-chip interconnects
Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
HLS code for Network on Chip (NoC)
Optimal circulant graphs generating results dataset
HLS for Networks-on-Chip
A Voting Approach for Adaptive Network-on-Chip Power-Gating
Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research
A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs
A demonstrator of Hermes network-on-chip communicating with the ARM processor
Development and simulation framework for Application Specific Vector Processor
Introduction about Embedded systems lab, University of Florida
System-on-Chip Interconnect Network Simulation Environment back-end (simulator)
A Vivado IP of Hermes network-on-chip router with AXI streaming interfaces
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