network-on-chip
Here are 40 public repositories matching this topic...
A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs
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Oct 30, 2017 - VHDL
Researching on Multi/Many-core Power-gating based on Network-on-Chip
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Dec 25, 2017
Research based implementation of a genetic algorithm for routing 'flits' in an NoC
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Feb 2, 2018 - C++
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
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Mar 19, 2018 - SystemVerilog
A Network-on-Chip for the System-of-Systems Era, Enabling mixed interface communication between embedded devices (MCU, sensors etc.) over a common protcol stack
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Jun 7, 2018 - VHDL
My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA
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Jun 26, 2018 - Verilog
Real-Time Network-on-chip Analysis and Simulation
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Jul 25, 2018 - Java
Convolutional Neural Networks for Verilog High-Level Synthesis
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Oct 19, 2018
System-Verilog implementation of the ACDMA crossbar
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Nov 25, 2018 - SystemVerilog
Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
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Jan 28, 2019 - C++
System-on-Chip Interconnect Network Simulation Environment back-end (simulator)
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Sep 26, 2019 - C++
Example of hardware trojan in a router detected with formal property verification
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Oct 21, 2019 - VHDL
Development and simulation framework for Application Specific Vector Processor
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Mar 8, 2020 - C++
Vivado test IP for Hermes NoC Router
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Jun 22, 2020 - VHDL
Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface
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Aug 8, 2020 - Tcl
A 2x2 mesh NoC compatible with AXI streaming interface
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Aug 8, 2020 - Coq
A demonstrator of Hermes network-on-chip communicating with the ARM processor
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Aug 10, 2020 - Tcl
HLS code for Network on Chip (NoC)
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Sep 11, 2020 - C++
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