A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
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Updated
May 24, 2024 - Verilog
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
Secure Multi-Party Computation (MPC) with Go. This project implements secure two-party computation with Garbled circuit protocol.
Hello there, welcome! This is a JavaScript algorithm that solves the 4x4 Karnaugh map. It is expandable to solve 2 and 3 variable tables as well, although it needs some slight changes not done yet.
A JavaScript API to (visually) manage logical circuits
UNI S3: a single digit logical ( BCD to 7Segment ) counter in Proteus
Windows console application for validating truth tables
Train ticket vending machine application designed for execution on an FPGA system. The application allows users to purchase tickets for various destinations and includes maintenance functionalities.
Logical circuits course final project.
Embedded domain-specific combinator library for the abstract assembly and automated synthesis of logical circuits.
This is my final project in the Logical Circuits course. In this project we designed a Smart Home Management System.
My Logical Circuits course Final Project - Fall98(2019) - VERILOG
✔️ Bit, Bytes and Logical Gates Abstraction
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