S3LC02

Our logic circuits course final project at CEIT.

Name		Name	Last commit message	Last commit date
Latest commit History 65 Commits
Module-1		Module-1
Module-2		Module-2
Module-3		Module-3
Module-4		Module-4
Module-5		Module-5
Module-6		Module-6
Module-7		Module-7
ModuleSmartHomeSystem		ModuleSmartHomeSystem
README.md		README.md

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