#
fusesoc
Here are 28 public repositories matching this topic...
VeeR EL2 Core
fpga
processor
riscv
rtl
risc-v
open-source-hardware
fusesoc
verilator
riscv32
western-digital
axi4
ahb-lite
asic-design
el2
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Updated
May 24, 2024 - SystemVerilog
NES Controller Interface written in Verilog-2005
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Updated
Mar 18, 2024 - Verilog
A quick SPI BFM to assist in SPI device testing and development
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Updated
Jan 15, 2024 - SystemVerilog
A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
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Updated
Aug 2, 2023 - Makefile
VeeR EH1 core
fpga
processor
riscv
rtl
risc
risc-v
open-source-hardware
fusesoc
verilator
riscv32
western-digital
axi4
ahb-lite
asic-design
veer
-
Updated
May 29, 2023 - SystemVerilog
A simple SHA-256 implementation in VHDL and Verilog, simulated using a basic UVM testbench.
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Updated
Oct 23, 2022 - Verilog
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