This repository contains source code for past labs and projects involving FPGA and Verilog based designs
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Updated
Oct 2, 2019 - Verilog
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
Binary Adder using RNN in Keras
Demonstration of the Content Scramble System (CSS) cryptosystem utlized on commercial DVDs
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
VHDL codes for 8-bit Vending Machine Processor, support for two drinks & three types of coins. contains: fsm, Accumulator, comparator, subtractor, mux, Adder, etc.
A 4bit Multiplier in VHDL
Binary adder implementation in the Game of Life written in JavaScript using canvas.
Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/
An adder is a digital circuit that performs addition of numbers. Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is designated as S which is SUM.
Testers for some non elementary integrated circuits: Adder 74283, D Flip-Flop 74174 & Counter 74193 written to be run from PSoC 4
CSE-2112 Digital Syatem Design LAb
Sumador de dos números de dos dígitos cada uno codificados en ASCII estándar en 7 bits. Restricción: realizar la suma en binario natural.
This is Amirkabir University Logic Circuit Design final project 2022
Progetto di Elettronica Digitale AA 2022-2023
Full adder implementation in Cyclone IV E - EP4CE115F2CBL FPGA
My solutions to 5 exercises of IBM quantum challenge 2020. Topics include quantum full-adder circuit implementation, circuit optimization and solving various puzzles using Grover's search algorithm.
Useful VHDL scripts for hardware description.
Digital Circuits made with VHDL
Digital Systems and Computer Structure, Simulation 1, Spring 2022
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