#

frquency-divider

Here is 1 public repository matching this topic...

ranjith-dhananjaya / 20GHz-integer-N-PLL-in-65nm-CMOS-process

Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process

design analog locking capacitor inductor pll vco pfd ic-design-project charge-pump frquency-divider

Updated May 5, 2022

Improve this page

Add a description, image, and links to the frquency-divider topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the frquency-divider topic, visit your repo's landing page and select "manage topics."