Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classification, detection, and segmentation problem.

Convolutional accelerator kernel, target ASIC & FPGA

A FPGA Based CNN accelerator, following Google's TPU V1.

A DNN Accelerator implemented with RTL.

hardware design of universal NPU(CNN accelerator) for various convolution neural network

Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.

Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.

Modified version of the "Explore the energy-efficient dataflow scheduling for neural networks. "

A CNN processor that takes layers of CNN as input instruction and performs the respective operation.

This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model architecture.