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Make simulations work for times longer than given by an
int32
time.
#445
opened Mar 28, 2024 by
tomcl
Changes to ram files are not picked up when stopping and restarting step simulator
#440
opened Mar 16, 2024 by
tomcl
Combinational Verilog component UI has missing confirmation on cancel dialog
#265
opened Dec 11, 2022 by
tomcl
New Issie custom components with program-defined internal hardware content
#199
opened Jul 24, 2022 by
tomcl
Unable to run dev when file path to Issie repo includes spaces on Windows
#166
opened May 18, 2022 by
adidesh20
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Updated in the last three days: updated:>2024-05-27.