Jetson start #209
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Jetson start #209
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- boots from eNVM - uses lim memory for RAM - has console on uart 0 - has procfs enabled - has most of nsh commands enabled Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
- Change git repository urls to point to our tiiuae repos for nuttx & nuttx apps - Remove most of the the build steps, leave just arm-12 and riscv; arm-12 has a build for stm32f7, and riscv for mpfs Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
…ptimized version in tiiuae repo Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
…iver to re-initialize on rx timeout If the interface is UP, and no packets are received in 30s, re-initialize the interface by calling the already implemented mpfs_txtimeout_expiry. This is a temporary workaround for a bug where IF might be UP and working but packets can only be transmitted. Receive side just doesn't work at all. The original bug can be re-produced easily by disconnecting and reconnecting the ethernet cable while the IF is up. Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
SD-card clock speed is just forced to 50MHz. Note that to be correct, one should first set the SD-card into high-speed mode, but currently NuttX doesn't support this. With our cards, just setting the interface to 50MHz seems to work fine, and it removes the issue with 25MHZ clock causing disturbance on GPS bands. Typically cards which support high-speed mode just work with 50MHz interface clock. This patch should be reverted when the NuttX supports high-speed mode, and we can properly set it. Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
…ootloader This removes the need to have all the DDR/clock configuration related "LIBERODEFS" flags defined, when not building a standalone/coldboot configuration All of this code is unused when not building with CONFIG_MPFS_BOOTLOADER Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This is not the correct way to do this, but it gives a nice perf. boost
Disable macOS builds for now.
All other commands are disabled in send_recv(). Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
…ef and forward declare devif_loopback Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
… that takes care of the need for loopback
Remove unnecessary VQID shifting (16 -> 0). Give an error if RPTUN init fails.
Enable LINUX_ON_HART4 in rpmsg-ch2 defconfig of ICICLE board. Remove LINUX_ON_HART4 config from rpmsg-ch1 defconfig of ICICLE board.
Fix build warning when CONFIG_STM32F7_AUTONEG is not set Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
…ved IO area in protected build Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Just a temporary patch, need to implement some kind of scalable solution for this. It might be a good idea to map something else for the user to avoid using ecall to enter the kernel for simple reads ? Also, increase the L3 table size
After this, RISC-V fully supports the kmap interface. Due to the current design limitations of having only a single L2 table per process, the kernel kmap area cannot be mapped via any user page directory, as they do not contain the page tables to address that range. So a "kernel address environment" is added, which can do the mapping. The mapping is reflected to every process as only the root page directory (L1) is copied to users, which means every change to L2 / L3 tables will be seen by every user.
The macro LOG2_CEIL is intended to be used in the pre-processor phase. If
used run-time it will generate a massive amount of extra code (~3.5K) which
is a problem, as the PMP configuration is quite often executed from a first
stage bootloader with a limited amount of code memory.
Code size differences pre- and post:
Memory region Used Size Region Size %age Used
envm: 112064 B 112384 B 99.72%
Memory region Used Size Region Size %age Used
envm: 108952 B 112384 B 96.95%
…orrectly [REVERTME] This patch is a stripped version from upstream, there are too many changes to the changed modules (would need to pull dozens of commits) so only the RISC-V elf linker is updated. There is a problem with the current elf loader for risc-v: when a pair of PCREL_HI20 / LO12 relocations are encountered, it is assumed that these will follow each other immediately, as follows: label: auipc a0, %pcrel_hi(symbol) // R_RISCV_PCREL_HI20 load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S With this assumption, the hi/lo relocations are both done when a hi20 relocation entry is encountered, first to the current instruction (addr) and to the next instruction (addr + 4). However, this assumption is wrong. There is nothing in the elf relocation specification[1] that mandates this. Thus, the hi/lo relocation always needs to first fixup the hi-part, and when the lo-part is encountered, it needs to find the corresponding hi relocation entry, via the given "label". This necessitates (re-)visiting the relocation entries for the current section as well as looking for "label" in the symbol table. The NuttX elf loader does not allow such operations to be done in the machine specific part, so this patch fixes the relocation issue by introducing an architecture specific cache for the hi20 relocation and symbol table entries. When a lo12 relocation is encountered, the cache can be consulted to find the hi20 part. [1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
Set HPWORK as default workqueue for eth ISR work
Previously, address 0x03b70000u was written with shift bits that only changed the bit width, not the mode. HS mode is changed via 0x03B90100, which is required, according to Jedec specs, for DDR mode. HS mode was not applied before. Enforce DDR mode (50 MHz) for now. The real boost, however, comes from removing the DMA limitation at 0x08xxxxxx address space, which now seems unnecessary. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Set the LOCKED bit when the final ddr segmentatition is in place. Otherwise the system is prone to potential security issues if the config is altered later. Once the LOCKED bit is set, the register may no longer be changed. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Replace risky DEBUGASSERT()s with real sanity checks. Also, do a few more checks as the system might occasionally fire an interrupt if the system has been restarted while in middle of an i2c transaction. Yet, modify i2c_transfer() function so that up_disable_irq() is always called at the end to better prevent ill-timed irqs. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Add a static port-based VLAN configuration for KSZ9477 switch. This doesn't use the VLAN tagging, but is a switch's internal mechanism to simply configure if the packet forwarding is allowed from one port to another. Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Move log2ceil from riscv_pmp to libc. Also, implement log2floor for completeness. These are the run-time alternative to the compile-time macros.
DMA directly to user (virtual) memory won't work, as the DMA engine(s) don't do address translations, i.e. they require a physical address. Using kernel heap is fine as it is mapped vaddr=paddr. Also, the USB DMA engine does not have any alignment requirements.
The hack just opens the entire SoC memory unconditionally, which is not a good idea. Test features can be used ad-hoc, they don't need to be supported by the build.
Fix the issue where fat driver is not using the last two clusters in the file system. The fat parameter fs->fs_nclusters is the maximum number of data clusters; this doesn't include the two in the beginning. Many checks in the fat driver treat the fs->fs_nclusters-1 as being the last accessible cluster, which is not right, the last accessible one is actually this number + 2 when the cluster count includes the two first ones. Normally this is not an issue when writes are being done through the same driver, the last two clusters are just never used. But if the filesystem is modified by external driver, for example with a populated fat created with PC, or modifying the FS via USB-MSC, this leads to the fat driver not being able to read anything that uses the last two clusters. Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Remove unnecessary junk, just build icicle (we don't care about the rest)
Don't use the upstream build targets
MPUCFG registers are used to enforce memory protection for DMA master devices.
This is not the right place to modify DMA memory protection values. Why not? These are designed to protect other AMP mode instances. Opening the entire SoC's memory for the USB DMA kind of defeats this purpose. Also, the driver cannot know how to configure these registers correctly, only opening up the whole SoC "works".
Add method to lock an MPUCFG entry. Locking means the value of the register cannot be changed until the SoC is reset.
…g/deinitializing bus Ensure that there are no pending state or interrupts in the i2c controller. This removes errors caused by deinitialize/initialize sequences in error cases. Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Add more error status codes to help debugging in the future. Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
- Use mpfs_i2c_deinit+mpfs_i2c_init sequence to re-initialize i2c block - Use the i2c mutex to protect the reset; in case there are several devices on the same bus, and one of them resets the bus, reset must not occur in the middle of another device's transfer. - Move irq attach to the i2c_init as the irq detach is in i2c_deinit Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Add sanity checks for debugging possible errors in the driver. Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
…s in warm boot Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
It is possible that a PLIC IRQ is claimed but not completed at warm reset. This occurs at least if there is a fault in the middle of irq handler execution. To recover from such situation, we can complete all IRQ:s in PLIC; this completes any already claimed IRQ, but has no effect on IRQs which are not claimed or not enabled. Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
… KConfigs Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
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Summary
This is more or less an "empty" arm64 nuttx configuration for "jetson-nano:nsh"
It compiles, but parts of uart driver is stubbed and jetson_boot.c contains some garbage addresses
To compile, take a compiler e.g. from here:
https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz?rev=9d9808a2d2194b1283d6a74b40d46ada&hash=F089155D2232ED5D4797B1F7808A70E4
Set the compiler to path:
export PATH=$PATH:<my_path>/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf/bin/
Configure nuttx:
./tools/configure.sh jetson-nano:nsh
Build:
make