Wolv Z1 CPU core supports currently only riscv32-imcb instruction set architecture and is implemented with 3-stage pipeline and Neumann bus architecture.
Cycles | Dhrystone/s/MHz | DMIPS/s/MHz | Iteration |
---|---|---|---|
336 | 2975 | 1.69 | 1000 |
Cycles | Iteration/s/MHz | Iteration |
---|---|---|
339742 | 2.94 | 10 |
Documentation will be expanded in the future.