Studies in Verilog
This repository features multiple necessary circuitry for any Computer System Organization. The files include:
- mux2to1.v
- A 2 to 1 mutiplexer
- mux4to1.v
- A 4 to 1 multiplexer made from 2 to 1 multiplexers
- mux7to1.v
- A 7 to 1 multiplexer implemented with an always block
- hex_display.v
- A Hexadecimal Display Decoder from Karnaugh Maps
- four_bit_ripple_carry_adder.v
- A 4-bit ripple carry adder
- arithmetic_logic_unit.v
- An Arithmetic Logic Unit (ALU)
- alu_register.v
- An ALU that stores the result into a register and uses the registered output as an input to next operation
- shifter.v
- A shifter circuit with arithmetic shift and parallel assignment options implemented with flipflops
- counter.v
- A 4-bit counter with t-flipflops
- automatic_counter_rate_divider.v
- A Rate Divider that slows down an automatic counter from 50Hz to 1Hz, 0.5Hz and 0,25Hz
- morse_encoder.v
- A morse encoder with rate divider
- sequence_detector.v
- A Finite State Machine that detects the sequence 1101 or four consecutive 1s (1111 or 111111)
- poly_function.v
- Calculates the value of the polynomial Ax^2 + Bx + C with a intercommunicating datapath and control unit
- ram32x4.v
- Simulates a 32x4 Random Access Memory
- square_animation.v (in VGA_monitor_projects folder)
- Animates a colored square bouncing around the screen