Single-Cycle-Risc-Processor-32-bit-Verilog

Trying to implement a single cycle MIPS computer in Verilog that supports MIPS assembly instructions including:

Memory-reference instructions load word lw and store word sw
Arithmetic-logical instructions add, addi, sub, and, andi, or, and slt
Jumping instructions branch-equal beq and jump j

Below image is the Risc processor I am trying to impleent, But end product may not be exactly the same.
img_src: Click Here

Name		Name	Last commit message	Last commit date
Latest commit History 42 Commits
README.md		README.md
alu.v		alu.v
alu_add_only.v		alu_add_only.v
alucontrol.v		alucontrol.v
branch_shiftleft2.v		branch_shiftleft2.v
choose_cathode.v		choose_cathode.v
control.v		control.v
data_memory.v		data_memory.v
dff_asy.v		dff_asy.v
divide_by_100k.v		divide_by_100k.v
divide_by_500.v		divide_by_500.v
instruction_memory.v		instruction_memory.v
jump_shiftleft2.v		jump_shiftleft2.v
mux_N_bit.v		mux_N_bit.v
program_counter.v		program_counter.v
register_file.v		register_file.v
ring_counter4.v		ring_counter4.v
sign_extension.v		sign_extension.v
single_cycle.jpg		single_cycle.jpg
single_cycle.png		single_cycle.png
single_cycle.v		single_cycle.v
single_cycle_rtl.jpg		single_cycle_rtl.jpg
single_cycle_tb.v		single_cycle_tb.v
ssd_driver.v		ssd_driver.v

sudhamshu091/Single-Cycle-Risc-Processor-32-bit-Verilog