fpga-vga

Little FPGA project. Play Pong on a VGA monitor :) Written in Verilog, developed using open source tools and hardware.

Hardware components

• FPGA: Lattice iCE40UP5K on iCEBreaker v1.0e Development Board
• Pmod VGA from Digilent (Schematic)
• Standard VGA monitor and cable

Design

My design consists out of two major modules. vga.v generates the vsync and hsync pulses, derived from internal vertical and horizontal counters (x_o and y_o). According to the current (x_o,y_o) position of the scanning process, main.v outputs the correct RGB values for that individual pixel.

VGA

Since VGA (Video Graphics Array) uses purely analog RGB signals, some additional hardware is needed. The VGA Pmod contains 3.3V bus drivers and simple 4-bit R-2R resistor DACs, one per color channel. This allows the proper signals expected by a VGA monitor to be generated by the FPGA. My implementation supports the standard 640x480@60Hz mode.

Timing

Update frequency
Screen refresh rate	60 Hz
Vertical refresh	31.47 kHz
Pixel frequency	25.175 MHz

Horizontal timing (line)

Scanline part	Pixels	Time [us]
Visible area	640	25.42
Front porch	16	0.6356
Sync pulse	96	3.813
Back porch	48	1.907
Whole line	800	31.78

Vertical timing (frame)

Scanline part	Pixels	Time [us]
Visible area	480	15253
Front porch	10	317.8
Sync pulse	2	63.56
Back porch	33	1049
Whole frame	525	16683

References

• Pmod VGA Reference Manual (Digilent)
• Pmod VGA Schematic (Digilent)
• TinyVGA VGA Timing specification
• Wikipedia: Video Graphics Array
• Youtube: Ben Eater, The world's worst video card?

Remarks

This project is the result of the P&S Course "iCEBreaker FPGA For IoT Sensing Systems (227-0085-28P)" at ETH Zürich.