It's just a simple testbench generator to test the VHDL implementation of the project 051228-Prova finale (progetto di reti logiche) held at Politecnico di Milano.
A "C pseudorandom generator" of VHDL testbenches for Digital Systems Design project at Politecnico di Milano.
License
ste7en/Project-Reti-Logiche-Testbench-Generator
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
About
A "C pseudorandom generator" of VHDL testbenches for Digital Systems Design project at Politecnico di Milano.
Topics
Resources
License
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published