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67 Open 184 Closed
67 Open 184 Closed
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Issues list

Give more useful error when using wrong java version and trying to parse resource models
#317 opened Dec 15, 2021 by mattfel1
Add support for chisel codegen of Vectors
#313 opened Oct 19, 2020 by pyprogrammer
Categorical HM integration with Spatial kernel implementations
#309 opened Jun 15, 2020 by mattfel1
2
Add Multiplicative Syntax for DSE Annotations
#308 opened Jun 15, 2020 by mattfel1
Confirm Banking with II = 1 is correct for two accesses scheduled at different cycles
#304 opened May 7, 2020 by mattfel1
Access patterns with specific cases of || and &&
#303 opened Mar 25, 2020 by mattfel1
Performance bug with loadCSV1D
#302 opened Mar 12, 2020 by kelayamatoz
@kelayamatoz
Throw Error if DRAMHost is declared inside accel good first issue Good for newcomers help wanted Extra attention is needed
#301 opened Mar 11, 2020 by mattfel1
AXI4 Compatibilty Issue
#299 opened Mar 2, 2020 by kelayamatoz
@kelayamatoz @mattfel1
Switch Transformer Potential Issue
#297 opened Feb 22, 2020 by mattfel1
Implement Dual Read Ports
#295 opened Feb 21, 2020 by mattfel1
@mattfel1
Disable optimized reduce for FltPt for now
#292 opened Feb 1, 2020 by mattfel1
Sketchy Resource Result for Memory
#291 opened Jan 28, 2020 by mattfel1
Port FrameIn/Out to cpp backend good first issue Good for newcomers help wanted Extra attention is needed
#289 opened Dec 11, 2019 by mattfel1
Optimize datapath bitwidths good first issue Good for newcomers help wanted Extra attention is needed
#288 opened Dec 11, 2019 by mattfel1
7
Compilation error with Zynq fpag
#279 opened Oct 29, 2019 by tissue3
7
Is there anyway to just generate verilog design?
#277 opened Oct 27, 2019 by tissue3
1
Random Unwanted DRAM Requests in Rogue App
#276 opened Oct 25, 2019 by mattfel1
Broadcast + CSE = Malformed Memory
#274 opened Oct 16, 2019 by mattfel1
Banking Analyzer is Lying About Being Able to Bank This
#273 opened Oct 16, 2019 by mattfel1
Not Staging Return Value of IfThenElse
#271 opened Sep 28, 2019 by mattfel1
Add support for LockSRAM and Lock nodes
#270 opened Sep 26, 2019 by mattfel1
1
ChiselGen is missing FltFMAAccum
#266 opened Aug 30, 2019 by kelayamatoz
@kelayamatoz
ChiselGen embeds wrong binary format of float
#265 opened Aug 27, 2019 by kelayamatoz
@kelayamatoz
accessIterators missing mem's iterators
#264 opened Aug 21, 2019 by kelayamatoz
@kelayamatoz
ProTip! Find all open issues with in progress development work with linked:pr.