RISC-V Single Cycle Datapath Verilog Implementation

Name		Name	Last commit message	Last commit date
Latest commit History 38 Commits
img		img
.gitignore		.gitignore
README.md		README.md
alu.v		alu.v
alu_control.v		alu_control.v
alu_control_tb.v		alu_control_tb.v
alu_tb.v		alu_tb.v
control_unit.v		control_unit.v
control_unit_tb.v		control_unit_tb.v
immediate_generator.v		immediate_generator.v
immediate_generator_tb.v		immediate_generator_tb.v
instruction_data.txt		instruction_data.txt
memory_unit.v		memory_unit.v
memory_unit_tb.v		memory_unit_tb.v
register_file.v		register_file.v
register_file_tb.v		register_file_tb.v
riscv.v		riscv.v
riscv_tb.v		riscv_tb.v

rykovv/riscv