riscvOVPsim Change Log
Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com
This CHANGELOG contains information for the riscvOVPsim fixed platform which includes information of the OVP Simulator and RISCV processor model
Date 2020-Jul-08
Release v20200708.0
- Reads of instret and cycle CSRs now exclude the current instruction from the
reported count. - The vector version master branch currently has these differences compared to
the previous 0.9 version:- SLEN=VLEN register layout is mandatory;
- ELEN>VLEN is now supported for LMUL>1;
- Whole register moves and load/stores now have element size hints;
- Instructions vfrsqrte7.v and vfrece7.v added, with candidate implementations
(precise behavior is not yet defined).