GitHub - reedv/Simple-MIPS-CPU: A simple pipelined MIPS CPU implemented in verilog. Can perform add, addi, beq, j, lw, and sw instructions.

reedv / Simple-MIPS-CPU Public

A simple pipelined MIPS CPU implemented in verilog. Can perform add, addi, beq, j, lw, and sw instructions.

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EE 361L-Lab5.pdf		EE 361L-Lab5.pdf

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A simple pipelined MIPS CPU implemented in verilog. Can perform add, addi, beq, j, lw, and sw instructions.

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