Skip to content

Commit

Permalink
Add ESIL for x86 SSE float instructions ##esil
Browse files Browse the repository at this point in the history
  • Loading branch information
@aemmitt-ns
aemmitt-ns committed Mar 22, 2022
1 parent db253ca commit 0be8f25
Showing 1 changed file with 150 additions and 16 deletions.
166 changes: 150 additions & 16 deletions libr/anal/p/anal_x86_cs.c
View file
Expand Up @@ -1818,10 +1818,6 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
}
break;
case X86_INS_MULX:
case X86_INS_MULPD:
case X86_INS_MULPS:
case X86_INS_MULSD:
case X86_INS_MULSS:
{
src = getarg (&gop, 1, 0, NULL, SRC_AR, NULL);
dst = getarg (&gop, 0, 1, "*", DST_AR, NULL);
Expand All @@ -1841,6 +1837,7 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
esilprintf (op, "%s,%s", src, dst);
}
break;

case X86_INS_NEG:
{
ut32 bitsize;
Expand Down Expand Up @@ -1948,24 +1945,119 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
#else
case X86_INS_FADDP:
#endif
{
ut32 bitsize;
src = getarg (&gop, 1, 0, NULL, SRC_AR, NULL);
dst = getarg (&gop, 0, 0, NULL, DST_AR, &bitsize);
esilprintf (op, "%u,%u,%s,F2D,%u,%s,F2D,F+,D2F,%s,=",
bitsize, bitsize, src, bitsize, dst, dst);

break;
}
break;
case X86_INS_ADDPS:
case X86_INS_ADDSD:
case X86_INS_ADDSS:
case X86_INS_ADDSUBPD:
case X86_INS_ADDSUBPS:
case X86_INS_SUBPS:
case X86_INS_SUBSS:
case X86_INS_MULPS:
case X86_INS_MULSS:
case X86_INS_DIVPS:
case X86_INS_DIVSS:
{
char operator = '+';
switch (insn->id) {
case X86_INS_SUBSS:
case X86_INS_SUBPS:
operator = '-';
break;
case X86_INS_MULSS:
case X86_INS_MULPS:
operator = '*';
break;
case X86_INS_DIVSS:
case X86_INS_DIVPS:
operator = '/';
break;
case X86_INS_ADDSUBPS:
case X86_INS_ADDSS:
case X86_INS_ADDPS:
default:
operator = '+';
break;
}
src = getarg (&gop, 1, 0, NULL, SRC_AR, NULL);
dst = getarg (&gop, 0, 0, NULL, DST_AR, NULL);
esilprintf (op, "32,32,%s,F2D,32,%s,F2D,F%c,D2F,%s,=",
src, dst, operator, dst);
}
break;
case X86_INS_ADDSUBPD:
case X86_INS_ADDSD:
case X86_INS_ADDPD:
// The OF, SF, ZF, AF, CF, and PF flags are set according to the
// result.
if (INSOP(0).type == X86_OP_MEM) {
case X86_INS_SUBSD:
case X86_INS_SUBPD:
case X86_INS_MULSD:
case X86_INS_MULPD:
case X86_INS_DIVSD:
case X86_INS_DIVPD:
{
char operator = '+';
switch (insn->id) {
case X86_INS_SUBSD:
case X86_INS_SUBPD:
operator = '-';
break;
case X86_INS_MULSD:
case X86_INS_MULPD:
operator = '*';
break;
case X86_INS_DIVSD:
case X86_INS_DIVPD:
operator = '/';
break;
case X86_INS_ADDSUBPD:
case X86_INS_ADDSD:
case X86_INS_ADDPD:
default:
operator = '+';
break;
}
src = getarg (&gop, 1, 0, NULL, SRC_AR, NULL);
dst = getarg (&gop, 0, 0, NULL, DST_AR, NULL);
esilprintf (op, "%s,%s,F%c,%s,=", src, dst, operator, dst);
}
break;
case X86_INS_RCPSS:
case X86_INS_RCPPS:
{
src = getarg (&gop, 1, 0, NULL, SRC_AR, NULL);
src2 = getarg (&gop, 0, 0, NULL, SRC2_AR, NULL);
dst = getarg (&gop, 0, 1, NULL, DST_AR, NULL);
esilprintf (op, "%s,%s,+,%s", src, src2, dst);
} else {
esilprintf (op, "32,32,%s,F2D,1,I2D,F/,D2F,%s", src, dst);
}
break;
case X86_INS_SQRTSS:
case X86_INS_SQRTPS:
{
src = getarg (&gop, 1, 0, NULL, SRC_AR, NULL);
dst = getarg (&gop, 0, 1, "+", DST_AR, NULL);
esilprintf (op, "%s,%s", src, dst);
dst = getarg (&gop, 0, 1, NULL, DST_AR, NULL);
esilprintf (op, "32,32,%s,F2D,SQRT,D2F,%s", src, dst);
}
break;
case X86_INS_RSQRTSS:
case X86_INS_RSQRTPS:
{
src = getarg (&gop, 1, 0, NULL, SRC_AR, NULL);
dst = getarg (&gop, 0, 1, NULL, DST_AR, NULL);
esilprintf (op, "32,32,%s,F2D,SQRT,1,I2D,F/,D2F,%s", src, dst);
}
break;
case X86_INS_SQRTSD:
case X86_INS_SQRTPD:
{
src = getarg (&gop, 1, 0, NULL, SRC_AR, NULL);
dst = getarg (&gop, 0, 1, NULL, DST_AR, NULL);
esilprintf (op, "%s,SQRT,%s", src, dst);
}
break;
case X86_INS_ADD:
Expand Down Expand Up @@ -2001,9 +2093,51 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
case X86_INS_STD:
esilprintf (op, "1,df,:=");
break;
case X86_INS_SUBSD: //cvtss2sd
case X86_INS_CVTSS2SD: //cvtss2sd
case X86_INS_CVTSS2SI:
case X86_INS_CVTSD2SI:
case X86_INS_CVTSD2SS:
case X86_INS_CVTSS2SD:
case X86_INS_CVTSI2SS:
case X86_INS_CVTSI2SD:
case X86_INS_CVTPS2PI:
case X86_INS_CVTPD2PI:
case X86_INS_CVTPD2PS:
case X86_INS_CVTPS2PD:
case X86_INS_CVTPI2PS:
case X86_INS_CVTPI2PD:
{
src = getarg (&gop, 1, 0, NULL, SRC_AR, NULL);
dst = getarg (&gop, 0, 1, NULL, DST_AR, NULL);

switch (insn->id) {
case X86_INS_CVTSS2SI:
case X86_INS_CVTPS2PI:
esilprintf (op, "32,%s,F2D,D2I,%s", src, dst);
break;
case X86_INS_CVTSD2SI:
case X86_INS_CVTPD2PI:
esilprintf (op, "%s,D2I,%s", src, dst);
break;
case X86_INS_CVTSD2SS:
case X86_INS_CVTPD2PS:
esilprintf (op, "32,%s,D2F,%s", src, dst);
break;
case X86_INS_CVTSS2SD:
case X86_INS_CVTPS2PD:
esilprintf (op, "32,%s,F2D,%s", src, dst);
break;
case X86_INS_CVTSI2SS:
case X86_INS_CVTPI2PS:
esilprintf (op, "32,%s,I2D,D2F,%s", src, dst);
break;
case X86_INS_CVTPI2PD:
case X86_INS_CVTSI2SD:
default:
esilprintf (op, "%s,I2D,%s", src, dst);
break;
}
break;
}
case X86_INS_BT:
case X86_INS_BTC:
case X86_INS_BTR:
Expand Down

0 comments on commit 0be8f25

Please sign in to comment.